Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1997-10-31
2000-09-19
Follansbee, John A.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 11, 712 14, 712 16, 712 37, 709220, G06F 1500
Patent
active
061227196
ABSTRACT:
A method and an apparatus for retiming in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected delay registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element. The first and second multiplexers are controlled to select one of a number of delay durations in response to the received set of data. A delay is programmed in the network structure in response to a data type being transferred between particular multiple context processing elements.
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Eslick Ian
French Robert
Mirsky Ethan
Follansbee John A.
Nguyen Dzung C.
Silicon Spice
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