Method and apparatus for results speculation under run-ahead...

Details Method and apparatus for results speculation under run-ahead... Method and apparatus for results speculation under run-ahead...

2003-12-17

2009-02-24

Treat, William M (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction fetching

Prefetching

Reexamination Certificate

active

07496732

ABSTRACT:
A method and apparatus for using result-speculative data under run-ahead speculative execution is disclosed. In one embodiment, the uncommitted target data from instructions being run-ahead executed may be saved into an advance data table. This advance data table may be indexed by the lines in the instruction buffer containing the instructions for run-ahead execution. When the instructions are re-executed subsequent to the run-ahead execution, valid target data may be retrieved from the advance data table and supplied as part of a zero-clock bypass to support parallel re-execution. This may achieve parallel execution of dependent instructions. In other embodiments, the advance data table may be content-addressable-memory searchable on target registers and supply target data to general speculative execution.

REFERENCES:
patent: 6944754 (2005-09-01), Zilles et al.
Sodani et al., “Dynamic Instruction Reuse”, Proceedings of the 24th annual international symposium on Computer architecture ISCA '97, vol. 25, Issue 2, May 1997, ACM, pp. 184-205.
Balasubramonian et al., “Dynamically allocating processor resources between nearby and distant ILP”, IEEE, Proceedings of the 28th Annual International Symposium onComputer Architecture, Jun. 30-Jul. 4, 2001, pp. 26-37.
Purser et al., “A study of slipstream processors”, MICRO-33. Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 10-13, 2000, pp. 269-280.

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