Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2002-03-04
2004-12-28
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06836420
ABSTRACT:
FIELD OF THE INVENTION
The field of invention relates generally to electronic circuit design; and more specifically, to a method and apparatus for a resetable memory and a design approach for same.
BACKGROUND
FIG. 1
shows a memory unit
101
. The memory unit
101
may be viewed as having a plurality of storage cells (or simply, “cells”). Associated with each cell is a unique address that provides access to the location of a particular storage cell. Each storage cell has the capacity to store “n” bits (where n is an integer greater than or equal to one). The n bits may be collectively referred to as a word of data.
Often, a memory unit
101
is written to by: 1) providing a word of data (i.e., “n” bits of data as seen in
FIG. 1
) to be written into the memory unit
101
on a data bus (such as input data bus
103
observed in FIG.
1
); 2) providing an address (e.g., on address bus
102
) that defines which storage cell will store the word of data; and 3) presenting a signal to the memory unit that effectively indicates the word of data on the data bus is to be written into the memory unit (such activating the write enable (WE) control line
104
of FIG.
1
).
Alternatively, the write could be time based as in a shift register, or it could be a mix of address and time based write.
Often, a memory unit
101
is read from by: 1) providing an address (e.g., on address bus
102
) that defines which cell a word of data will be read from; and 2) presenting a signal to the memory unit that effectively indicates a word of data is to be read from the memory unit (such as activating the read enable (RE) control line
130
of FIG.
1
). The word of data is presented at the data output bus
106
. In embodiments alternative to that observed in
FIG. 1
, the data in and data out buses
103
,
106
may be combined to form a bi-directional bus. Also, in various alternate embodiments, one of the enable lines
104
,
130
may be eliminated so that a single line is used to toggle the memory unit between being in a writable state and being in a readable state. Alternatively, it could be time based as in a shift register, or a mix of address and time based read. A commercial example that uses a mix of address and time based read/write is the Xilinx Virtex SRL primitive that is written into like a shift register and is read from like a RAM.
The memory unit
101
of
FIG. 1
can be used to implement a number of storage related devices such as a random access memory (RAM), a first-in-first-out (FIFO) queue (e.g., by appropriately controlling the address values of the memory unit
101
such that a FIFO queue is emulated with the memory unit
101
), a content addressable memory (CAM), a shift register, etc. A problem with memory units (as they are offered to designers who wish to employ them in their circuit designs), however, is that they do not have a reset function. A reset function effectively “clears” the memory unit's cell word values to some “reset” value (e.g., a n wide value of “0”); and, often, the integration of circuitry for resetting the cell word values of the memory unit
101
is too expensive and/or complicated to implement. For example, according to one approach, in order to implement a resetable memory, each n wide storage cell is implemented with resetable flip-flops that are individually accessed via complicated multiplexing and control circuitry. Here, the use of resetable flip-flops to implement each n wide storage cell (as well as the complicated multiplexing and control circuitry) can result in a resetable memory unit having noticeably slower performance (and that consumes more silicon surface area) than a memory unit that does not have resetable storage cells.
SUMMARY OF THE INVENTION
An apparatus is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupled to a resetable storage cell output that indicates whether a storage cell within the memory without reset capability has been written to after a reset or has not been written to after a reset.
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McElvain Kenneth S.
Seshadri Vijay K.
Blakely , Sokoloff, Taylor & Zafman LLP
Nguyen Viet Q.
Synplicity, Inc.
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