Dynamic magnetic information storage or retrieval – General processing of a digital signal – In specific code or form
Reexamination Certificate
2001-03-21
2004-06-01
Hudspeth, David (Department: 2651)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
In specific code or form
C360S039000, C360S055000, C714S792000, C714S796000
Reexamination Certificate
active
06744580
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and apparatus for reproducing data recorded on a recording medium and a method and apparatus for recording and/or reproducing data for a recording medium.
2. Description of Related Art
As a recording medium for recording digital data, there are known a wide variety of recording mediums of the magnetic, optical or photomagnetic system, such as a hard disc, a so-called DVCR (digital video cassette recorder) or a so-called CD (Compact Disc), DVD (digital versatile disc) and a so-called MO (magneto-optical disc).
For recording signals on these recording mediums, physical processing needs to be performed on the recording mediums, such as by controlling the direction of magnetization by a write head for a recording medium of the magnetic recording system, or by forming pits of lengths corresponding to signals by a stamper for a recording medium of the optical recording system. In this case, in order to permit amplitude control of readout signals or clock reproduction on the reproducing side reading out the signals recorded on the recording medium to operate as normally, the signal recording side for recording signals on a recording medium routinely uses a system of modulation encoding the signal in a pre-set manner to record the resulting modulation-coded signal.
A modulation-coder, performing this modulation coding, routinely is fed with binary signals exempt from various limitations, and outputs binary signals free of various limitations. These limitations on the signals include DC free limitations which state that the numbers of “0”s and “1”s be equalized over a sufficient long length of the concatenations of “0”s and “1”s, and the (d, k) limitations which state that the minimum and maximum numbers of consecutive “0”s and “1”s in a code be d and k, respectively.
FIG. 1
shows an input/output example in a modulation coder outputting a code satisfying the (d, k)=(2, 7) limitations. Specifically, a modulation coder
150
, outputting a code satisfying the (d, k)=(2, 7) limitation, is shown in
FIG. 1
, by way of concrete explanation of the concept of the (d, k) limitations. That is, if an input signal, free of the limitation, is input to the modulation coder
150
, outputting a code satisfying the (d, k)=(2, 7) limitation, modulation-encodes the input signal to generate and output an output signal in which the minimum and maximum numbers of consecutive “0”s are 2 and 7, respectively.
The above example indicates that, in converting a bit string free of a limitation is converted into another bit string subjected to a limitation, the total number of the output bits is larger than that of the input bits. If the total number of input bits is K and the total number of output bits is N, the ratio K/N is represented as a code rate R. This code rate R serves as an index indicating the efficiency of the modulation coding. If two or more modulation coders, generating output signals satisfying the same limitations, are compared to one another, a modulation coder having the high code rate R is able to encode more input bits for a given number of output bits than one having the low code rate R. Stated differently, a modulation coder having a high code rate R is able to record more information on a pre-set recording medium than one having a low code rate R.
The modulation coding may be classified into a block coding system in which input bits are divided into plural blocks of pre-set lengths and output bits generated are divided into plural blocks of pre-set lengths corresponding to the blocks of the input bits, and a variable length coding system, in which encoding units of input bits and output bits associated with the input bits are varied. For example, the so-called 8/9 code or the 16/17 code, routinely used for modulation coding, belong to the block coding system, whilst the so-called (1, 7) RLL code or the (2, 7) RLL code belong to the variable length encoding system.
For example, in a block modulation encoding system, fed with two bits as input bits, and generating three output bits satisfying the (d, k)=(0, 2) limitations, a modulation coder has a conversion table as Table 1:
TABLE 1
Example of Conversion Table
input bits
output bits
00
011
01
101
10
111
11
110
stored in e.g., a memory, not shown. The modulation coder references this conversion table and finds, for each 2-bit input bits, an associated 3-bit output bits, with the output bits being issued as output sequentially.
On the other hand, a modulation decoder for modulating-decoding the modulation-coded signals has a back-conversion table, as Table 2:
TABLE 2
Example of Back-Conversion Table
input bit
decoded bits
000
01
001
00
010
10
011
00
100
11
101
01
110
11
111
10
corresponding to the conversion table of Table 1, stored in e.g., a memory, not shown. The modulation decoder references this back-conversion table to find and sequentially output 2-bit decoded bits, associated with the 3-bit input bits.
FIG. 2
shows a typical modulation decoder
160
having at least a ROM (read-only memory)
161
. The modulation decoder
160
is fed with an input address signal D
161
to output the contents stored in an address of the ROM
161
corresponding to this input address signal D
161
as a demodulated decoded signal D
162
. In actuality, if the input bits are back-converted into decoded bits in accordance with the back-conversion table shown in Table 2, the contents of the decoded bits are stored in addresses of a ROM
161
of the modulation decoder
160
, corresponding to the input bits in Table 2. The decoded bits, stored in these addresses, are read out by way of performing the back-conversion.
FIG. 3
shows a typical modulation decoder
170
at least having a combination circuit
171
. The modulation decoder
170
is fed with an input signal D
171
and executes logical operations on the input signal D
171
by the combination circuit
171
to generate a modulated decoded signal D
172
. In actuality, if, in performing back conversion from the input bits to the decoded bits in accordance with the back-conversion table of Table 2, the three-bit input signal D
171
is represented as (a
0
, a
1
, a
2
) and a two-bit modulated decoded signal D
172
is represented as (b
0
, b
1
), the modulation decoder
170
generates the output bits (b
0
, b
1
) by the combination circuit
171
corresponding to the following logical equations (1):
b
0
=(
a
1
&
a
2
)|(
a
0
&!
a
1
&!
a
2
)|(!
a
0
&
a
1
&!
a
2
)
b
1
=(
a
0
&!
a
1
)|(!
a
0
&!
a
1
&!
a
2
)|(
a
0
&
a
1
&!
a
2
) (1)
where |, & and ! indicate the logical sum, logical product and logical negation, respectively.
If the modulation coder and the modulation decoder are applied to a magnetic recording and/or reproducing apparatus for recording and/or reproducing data on or from a recording medium in accordance with the magnetic recording system, the recording and/or reproducing apparatus is configured as shown in FIG.
4
.
That is, the magnetic recording and/or reproducing apparatus
200
, shown in
FIG. 4
, includes, as a recording system for recording data on a recording medium
250
, an error correction encoder
201
for error correction encoding input data, a modulation encoder
202
for modulation encoding the input data, a precoder
203
for filtering input data for compensating its channel characteristics, a write current driver
204
for converting respective bits of the input data into write current values, and a write head
205
for recording data on the recording medium
250
. The magnetic recording and/or reproducing apparatus
200
also includes, as a playback system for reproducing data recorded on the recording medium
250
, a readout head
206
for reading out data recording on the recording medium
250
, an equalizer
207
for equalizing the input data, a gain adjustment circuit
208
for adjusting the gain of the input data, an analog/digital converter (A/D conv
Hattori Masayuki
Miyauchi Toshiyuki
Murayama Jun
Figueroa Natalia
Frommer William S.
Frommer & Lawrence & Haug LLP
Hudspeth David
Kessler Gordon
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