Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-11-02
2001-10-09
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S023000, C703S019000, C716S030000, C714S724000
Reexamination Certificate
active
06301553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of circuit designs. More specifically, the present invention relates to the art of dealing with timing hazards when designing or validating circuits including level-sensitive storage circuit elements.
2. Background Information
In synchronous sequential circuits, the storage circuit elements (or registers) are basically controlled (or synchronized) by a periodic clock signal called the design source clock. The design source clock is very often combined with logic to generate derived clock signals such as gated or divided clocks. These derived clocks signals drive the input clock pin of the registers. The correct operation of the synchronous sequential circuit depends primarily on the fact that only transitions by the design source clock signal can cause register outputs to switch. Furthermore, when the design is implemented in hardware, the clock delay between the design source clock input and the input clock pins of the registers of the circuit must respect certain design tolerance constraints. More specifically, the clock skew, i.e. the difference between the input clock pin delay for two distinct registers, must be less than the time required to propagate data between these two registers. Otherwise, race conditions may be reached that will cause timing hazards such as hold time violations.
These timing hazard problems present themselves when designing or validating circuits in, for instance, cycle based simulation, hardware acceleration, and hardware emulation. The timing hazard problems are especially acute for hardware emulation, which is often employed to validate circuit designs prior to first silicon. Hardware emulation decreases the design development time by allowing a “real-time” verification ten thousand to one million times faster than software logic simulation. Thus, hardware emulation has become increasingly popular as complexity of circuit designs and the pressure to reduce time to market continue to increase.
A typical hardware emulation system includes a reconfigurable hardware emulator and circuit design “mapping” software which produces a hardware implementation of the circuit design to be emulated onto the hardware emulator system. This “mapping” software includes netlist translation, synthesis and technology mapping, and partitioning and routing for multiple electronically reprogrammable circuit based architectures, so that the mapping software can automatically produce a configuration file. The configuration file is downloaded to the hardware emulator to configure the emulator into a hardware prototype of the design. Unfortunately, all hardware emulators have limitations that constrain their performance. One of the most important problems involves meeting fundamental timing requirements of the original design, such as ensuring a minimal clock skew between registers controlled by clock signals directly connected or derived from the same design source clock input. Minimal clock skew ensures that a design operates properly by preventing hold time violations due to short paths between registers (latches or edge triggered flip-flops).
Existing hardware emulators typically provide a clock distribution network with zero-skew so that every register which is directly connected to such a distribution network can be clocked with a minimal clock skew. In existing hardware emulators, the design source clock signal is implemented by the clock distribution network so that the registers directly connected to the design source clock signal can behave properly, that is, without any hold time violations. The implementation of the design source clock by the clock distribution network will be referred to as “the master clock.”
When a clock is derived (gated or divided), the derived clock can no longer be routed over the clock distribution network. As a result, the minimal clock skew can no longer be guaranteed. Three techniques are commonly employed to solve this problem:
1) Hand patching of the original design to remove the gated and divided clocks.
2) Timing analysis of potential hold time violations and introduction of additional delays between registers after the partitioning and routing steps.
3) Pulling of the gated and divided clocks to the source of the clock distribution network.
These techniques suffer a number of drawbacks. The first technique is both time consuming and error prone. The second technique involves recompiling the design and may produce significant transformations in the circuit design, which in turn may result in new potential hold time violations and may lead to a time consuming compilation loop. The last technique is limited by the number of clock signals routed over the clock distribution network.
More recently, a new approach has been used to automatically solve the gated clock problem in the case of flip-flops that are controlled by a particular combinatorial logic gate set. In this approach, the structure of the gated clock combinatorial logic is identified. Then, the combinatorial logic is transformed so that the respective flip-flop is directly controlled by the master clock and the combinatorial logic provides a separate enable signal to the flip-flop. This approach, however, depends heavily on the way in which the clock signal is generated, i.e. the structure of the combinatorial logic. Furthermore, this approach is not applicable in the case of level sensitive storage circuit elements (i.e. latches).
As will be disclosed in more detail below, the present invention provides a new automated approach to remove timing hazards from a circuit design. The invention overcomes the prior art disadvantages, and provides a number of desirable advantages, which will be readily apparent to those skilled in the art. The invention is especially adaptable for use in a hardware emulator, although the invention is similarly applicable to cycle based simulation, hardware acceleration, etc.
SUMMARY OF THE INVENTION
An apparatus is programmed to automatically remove timing hazards from a circuit design. The apparatus identifies certain level sensitive storage circuit elements in the circuit design. The identified level sensitive storage circuit elements are those having timing hazards. The timing hazards arise as a result of skew, i.e. the difference in delay between the input clock pins of registers (one or both being a level sensitive storage circuit element). A skew, introduced by a gated or divided clock, cannot be assured to be within a design tolerance limit. Therefore, the program enables the apparatus to transform the identified level sensitive storage circuit elements so that each is directly controlled by the design source clock signal. Since the design source clock signal is mapped onto the clock distribution network, the apparatus allows the level sensitive storage circuit elements to behave properly. The transformation, however, is accomplished without altering the functionality of the circuit design. In effect, the apparatus automatically removes some or all of the timing hazards by determining the appropriate transformation for each of the identified level sensitive storage circuit elements. The apparatus can also be viewed as a way to minimize the number of clock signals within a design without altering the functionality.
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Burgun Luc M.
Emirian Frederic M.
Columbia IP Law Group, PC.
Phan Phai
Teska Kevin J.
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