Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-08-11
2001-10-09
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S230080, C365S194000
Reexamination Certificate
active
06301188
ABSTRACT:
BACKGROUND
The present invention relates generally to integrated circuits, and more particularly, to a method and apparatus for registering free flow information in integrated circuits.
Integrated circuits, such as synchronous circuits, are widely used in computer systems because information entered into the circuit can be processed quickly and made available as valid output information. One example of a synchronous circuit is a synchronous static random access memory (SRAM) device. Such synchronous memory devices are registered and accessed based on externally generated clock signals which provide for synchronous operation of the device.
Synchronous circuits such as synchronous SRAMs typically employ one or more input registers to capture information at the input terminals and to pass the information to core circuitry. A register may be implemented, for example, as a pair of latches.
Ideally, data presented to the inputs of a synchronous circuit should be available as reliable, valid data as soon as possible. In other words, the time between the appearance of the data at the inputs to the circuit and the appearance of a correct and stable output to the core circuitry should be as small as possible.
In addition, the output data should remain reliable and valid until processing of the data performed by the core circuit is completed. The details of such internal processing depend on the particular device or system in which the input data is to be used. For example, in a synchronous SRAM circuit, information from a register may be encoded and used to access individual memory cells for a read or a write operation. In a read operation, once the individual memory cells have been accessed, the data from the cells can be passed to other circuitry. Processing of the input data sometimes requires more than one system clock cycle.
Unfortunately, neither registers nor latches exhibit such ideal behavior. For example, data presented to the input of a register is sampled, stored and propagated through the register upon the occurrence of a rising edge of the system clock. Although the register holds the data appearing at its inputs for the duration of the clock cycle, the data is not captured by the register until the rising edge of the clock signal. In addition, the transparency is subject to a delay introduced by the response time of the individual components of the register.
Similarly, a latch allows input data to be passed through to the core circuitry, and captures the data, for example, on a rising edge of a system clock signal. The captured data is held by the latch until the occurrence of a falling edge of the clock signal, at which time the previously-held data is released by the latch.
FIG. 1
is a timing diagram which illustrates some disadvantages that are occasionally associated with registers and latches used to capture and propagate input data in synchronous SRAMs and similar devices. The illustrated signals include an external clock signal, an input data signal that appears at the input to a latch or register, and data signals appearing at the output of the latch and register, respectively. Upon the occurrence of a rising edge of the external clock signal at a time
10
, data appearing at the output of the latch becomes valid. However, data appearing at the output of the register does not become valid until a subsequent time
12
after the occurrence of the rising edge of the external clock signal. Therefore, a delay is introduced with respect to the availability of valid output data from the register. Upon the occurrence of a falling edge of the external clock signal at a time
14
, the data at the output of the latch is no longer valid. Processing of the captured data is not completed, however, until a later time
16
.
Therefore, it would be desirable to provide a technique in which input data can be captured and passed to SRAM or other core circuitry quickly and held as long as necessary until completion of processing by the core circuitry.
SUMMARY
In general, according to one aspect, a circuit, such as a synchronous SRAM, includes core circuitry for processing input signals. Multiple terminals are provided to the circuit for receiving, respectively, an input signal and an external clock signal. The circuit includes a latch for receiving the input signal and an internal clock signal. The latch has an output connected to the core circuitry and can operate in a latched state and an unlatched state. The circuit also includes an internal clock controller for receiving the external clock signal and for providing the internal clock signal to the latch to control transitions of the latch between the latched and unlatched states based on the external clock signal. In response to an external clock signal, the internal clock controller extends the period of time in which the latch operates in the latched state.
In another aspect, the circuit includes a terminal for receiving a control signal. The internal clock maintains the latch in the latched state for multiple cycles of the external clock in response to assertion of the control signal.
Various implementations of the circuit can include one or more of the following features. In general, input signals can include address, data or control signals that are to be processed or used by the core circuitry. The internal clock controller can include a delay circuit to provide a delayed version of the external clock signal. The delay circuit can include, for example, multiple inverters and can extend the period of time in which the latch operates in the latched state by a predetermined amount of time. In some implementations, the delay circuit extends the period of time in which the latch operates in the latched state by an amount of time based on the type of operation to be performed with respect to the input signal.
If the circuit is a synchronous SRAM, the SRAM core may include a memory array, an address decoder, write drivers, sense amplifiers and input/output buffers.
According to another aspect, a method of registering free flow information in a synchronous device includes receiving an input signal and an external clock signal in the device. The input signal is passed to a latch in the device, wherein the latch can operate in either a latched state or an unlatched state. The latch is caused to operate in the latched state. While in the latched state, the latch holds the input signal to make it available to core circuity in the device. An internal clock signal is provided to the latch in response to the external clock signal and causes the period of time that the latch operates in the latched state to be extended.
In another aspect, a method of registering free flow information in a synchronous device includes receiving an input signal, an external clock signal, and a control signal in the device. The input signal is passed to a latch in the device, wherein the latch can operate in either a latched state or an unlatched state. The latch is caused to operate in the latched state. While in the latched state the latch holds the input signal to make the input signal available to core circuity in the device. An internal clock signal is provided to the latch in response to the external clock signal and maintains the latch in the latched state for multiple cycles of the external clock in response to assertion of the control signal.
One or more of the following advantages are present in some implementations. The internal clock controller can ensure that the time between the appearance of signals at the inputs to the circuit and the appearance of a correct and stable output to the core circuitry is relatively small. In addition, the internal clock controller can ensure that the output data remains reliable and valid until the core circuit completes its processing of the data.
Although the internal clock controller can be particularly advantageous for use with a synchronous SRAM, the internal clock controller also can be provided as part of other devices and systems, including other synchronous or non-synchronous memory devices, microprocessor
Porter John D.
Thompson William N.
Weber Larren G.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Nguyen Tuan T.
Zarabian Amir
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