Patent
1995-06-30
1998-01-13
Treat, William M.
395393, G06F 900
Patent
active
057088373
ABSTRACT:
A method and apparatus for register renaming in a computer system are provided. A map table stores physical register addresses corresponding to architected register addresses. An aritmetic available queue stores addresses of physical register available for aritmetic. A load available queue stores addresses of physical register available for loads. A store queue stores a plurality of pending physical store addresses. An aritmetic store compare function compares a displaced physical register address with the plurality of store addresses for updating the aritmetic available queue. A load store compare function compares a freed physical register address with the plurality of store addresses for updating the load available queue. An instruction queue stores a plurality of pending source and target instruction addresses. A store queue compare function compares one of the plurality of pending store addresses with the target instruction addresses in the instruction queue for updating the load available queue and the aritmetic available queue.
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International Business Machines - Corporation
Maung Zarni
Pennington Joan
Treat William M.
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