Method and apparatus for register management using issue sequenc

Details Method and apparatus for register management using issue sequenc Method and apparatus for register management using issue sequenc

1995-09-01

1997-10-07

Lall, Parshotam S.

395392, 395591, G06F 938

Patent

active

056757590

ABSTRACT:
In a microprocessor, an apparatus is included for coordinating the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts source and destination logical registers from the instruction. For the destination logical register, the apparatus assigns a physical address to correspond to the logical register. In so doing, the apparatus stores the former relationship between the logical register and another physical register. Storing this former relationship allows the apparatus to backstep to a particular instruction when an execution exception is encountered. Also, the apparatus checks the instruction to determine whether it is a speculative branch instruction. If so, then the apparatus creates a checkpoint by storing selected state information. This checkpoint provides a reference point to which the processor may later backup if it is determined that a speculated branch was incorrectly predicted. Overall, the apparatus coordinates the use of physical registers in the processor in such a way that: (1) logical/physical register relationships are easily changeable; and (2) backup and backstep procedures are accommodated.

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