Method and apparatus for reducing transitions on computer signal

Details Method and apparatus for reducing transitions on computer signal Method and apparatus for reducing transitions on computer signal

1992-06-26

1997-07-22

Moore, David K.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395402, 395416, 3954211, 3652335, G06F 1314

Patent

active

056511264

ABSTRACT:
A method and apparatus for eliminating unnecessary address transitions on an DRAM address bus and DRAM write enable line. In a known DRAM controller and DRAM array, all address transitions on the CPU address bus are mirrored by address transitions on the DRAM address bus. The present invention eliminates all address transitions not associated with an actual DRAM access cycle by eliminating the DRAM controller's address multiplexer and replacing it with a multiplexing driver circuit and a bus holder circuit. In a similar fashion, a DRAM write enable circuit eliminates all transitions on the DRAM write enable line that are not associated with actual DRAM access cycles. Although specifically discussed in terms of a DRAM array and its associated circuitry, the portion of the present invention that reduces address transitions on the DRAM address lines could be used in any device currently using a multiplexer.

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