Method and apparatus for reducing the bias current in a referenc

Details Method and apparatus for reducing the bias current in a referenc Method and apparatus for reducing the bias current in a referenc

1997-09-25

1999-09-28

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327124, H03K 5153

Patent

active

059594713

ABSTRACT:
A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.

REFERENCES:
patent: 5473273 (1995-12-01), Warner et al.
patent: 5692025 (1997-11-01), Sato et al.
patent: 5699063 (1997-12-01), Takayma
patent: 5793231 (1998-08-01), Whittaker

Affiliated with

Also associated with

Rating

Method and apparatus for reducing the bias current in a referenc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for reducing the bias current in a referenc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing the bias current in a referenc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-707624