Method and apparatus for reducing the access time of a memory de

Details Method and apparatus for reducing the access time of a memory de Method and apparatus for reducing the access time of a memory de

1995-09-14

1997-04-29

Asta, Frank J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395427, 395432, 365203, 36523006, 36523008, 364DIG1, G06F 1200

Patent

active

056257902

ABSTRACT:
A memory device includes an array of memory cells that are arranged in rows and columns. A row address latch connected to the address bus stores a row address on the address bus during a precharge period responsive to a transition of a row address strobe from an active low state to an inactive high state. A row decoder connected to the row address latch decodes the stored row address, and a redundancy checker determines if the decoded row is defective and, if so, selects a redundant row of memory cells for addressing. The row address decoder and the redundancy checker perform these respective functions during the precharge period. The memory device also includes a wordline controller that fires a wordline corresponding to the addressed row responsive to a transition of the row address strobe from its inactive high state to its active low state. Significantly, the wordline can be fired almost immediately upon the transition of the row address strobe to its active state because the row address has already been decoded and the need for redundancy checked.

REFERENCES:
patent: 5268865 (1993-12-01), Takasugi
patent: 5327390 (1994-07-01), Takasugi
patent: 5412604 (1995-05-01), Fukuda et al.
patent: 5515322 (1996-05-01), Kondo
patent: 5519657 (1996-05-01), Arimoto
patent: 5528552 (1996-06-01), Kamisaki

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