Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter
Reexamination Certificate
2001-03-13
2002-11-12
Nguyen, Matthew (Department: 2838)
Electric power conversion systems
Current conversion
Including d.c.-a.c.-d.c. converter
Reexamination Certificate
active
06480401
ABSTRACT:
FIELD OF INVENTION
This invention relates to low-power power supplies, and more particularly to circuitry for varying both the ON time and the OFF time of the main current switch in a flyback converter type power supply when the load drops below a predetermined level, so as to reduce the power consumption of the power supply when the device being powered is in a “sleep” mode or turned off.
BACKGROUND OF THE INVENTION
The recent proliferation of rechargeable electronic equipment, such as mobile telephones, PDA's and notebook computers has dramatically increased the number of chargers connected to the public electricity supply. These chargers typically have no on/off switch and are frequently left permanently “plugged-in” to the wall socket. The “standby” power consumption (i.e., when the equipment is off and any batteries fully charged) of current technology chargers places a significant load on the public electricity supply. It has been estimated that in Europe, such chargers unnecessarily consume the equivalent of the output of three power stations. Environmental and economic considerations therefore make it desirable to significantly reduce the standby power of electronic equipment and chargers. In Germany, regulations known as “Blue Angel”, provide, for example, that cellular phone chargers or personal computers may not consume more than 0.5 W when the equipment is off (i.e., an open load), or 5 W when the equipment is in “sleep” mode.
Inexpensive low-power conversion systems such as those typically used in cell phone or laptop computer chargers usually use a simple and low-cost self-oscillation flyback converter topology. This type of converter uses pulse width modulation with a fixed OFF time and a variable ON time to accommodate the power requirements of the load. The lighter the load, the higher the switching frequency and hence the higher the switching loss. In conditions where the device is being powered in a “sleep” mode or turned off, the switching loss becomes substantial and needs to be remedied.
Conventionally, excessive switching loss is reduced by “burst mode” operation in which the pulse width modulator is randomly switched between an OFF mode and an ON mode. The burst rate is unpredictable and is affected by a number of factors, such as the loop response and other second-order circuit parameters. This method has several major problems:
1) The circuit consumes high power at no load and light load, especially before the “burst mode” operation is activated;
2) The unpredictable random “burst” operation may create electromagnetic interference and ripple problems;
3) The system has poor flexibility in setting the operational point at which power saving is initiated;
4) The response of a particular unit is difficult to control over a production spread; and
5) Audible noise is generated in “burst mode” operation.
The disadvantages of random “burst” operation have been addressed in U.S. Pat. Nos. 5,481,178, 5,731,694 and 5,994,885 to Wilcox, et al. In those patents, “burst” operation is still used, but the burst rate is dependent on the output capacitor and the offset current I
1
. The circuits of these patents have an off-time control but only for the purpose of limiting the switching frequency to keep it out of the audible range.
A need consequently still exists for a reliable, predictable, controllable and quiet power reduction circuit for standby-load or no-load conditions in low-power electronic power supplies.
SUMMARY OF THE INVENTION
The present invention fills the above-stated need by providing a circuit which operates as a conventional ON time modulator under normal load conditions, but switches to a dual mode modulation when the load is reduced to a predetermined level. In the dual mode, the circuit modulates both the ON time and the OFF time simultaneously in opposite directions. By setting the gain of the OFF time control higher than the gain of the ON time control, the switching frequency is reduced as the output power declines. Consequently, the circuit of the invention has the following advantages:
1) Input power is reduced at both no load and light load;
2) No audible noise due to lack of “bursts” under no-load conditions;
3) Predictable behavior at no load;
4) Cut-in level of power saving mode can easily be set by appropriate choice of component values and is therefore repeatable over the production spread; and
5) The circuit has better large-step load response due to the dual mode modulation.
REFERENCES:
patent: 5469349 (1995-11-01), Marinus
patent: 5481178 (1996-01-01), Wilcox et al.
patent: 5731694 (1998-03-01), Wilcox et al.
patent: 5920466 (1999-07-01), Hirahara
patent: 5994885 (1999-11-01), Wilcox et al.
patent: 5995384 (1999-11-01), Majid et al.
patent: 5995388 (1999-11-01), Preller
patent: 6104622 (2000-08-01), Shin
patent: 6288914 (2001-09-01), Sato
Philips Semiconductors (Product Brochure), “Product Specification TEA1523 STARplug+™,” Nov. 17, 1999, pp. 1-18.
SGS-Thomson Microelectronics (Product Brochure), “Full Integrated Power Supply Flips™, L6590,” Mar. 1998, pp. 1-8.
SGS-Thomson Microelectronics (Product Brochure), “Primary Controller with Standby, L5991, L5991A,” Aug. 1998, pp. 1-23.
Astec International Limited
Coudert Brothers LLP
Nguyen Matthew
LandOfFree
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