Method and apparatus for reducing standby current in communicati

Details Method and apparatus for reducing standby current in communicati Method and apparatus for reducing standby current in communicati

1996-11-07

1999-08-24

Chin, Wellington

Telecommunications

Receiver or analog modulated signal frequency converter

With particular receiver circuit

455208, 455259, 455265, 331 18, 375354, H04B 116

Patent

active

059436131

ABSTRACT:
A method and apparatus for reducing power consumption in a communication device. In a standby mode, a relatively high power clock with a high degree of accuracy is powered down and a lower power, low frequency clock is used to maintain system synchronization. Synchronization means are provided to improve the accuracy of the low frequency clock during the standby mode.

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patent: 5416435 (1995-05-01), Jokinen et al.
patent: 5448755 (1995-09-01), Tanaka
patent: 5493700 (1996-02-01), Hietala et al.
patent: 5511235 (1996-04-01), Duong et al.
patent: 5548250 (1996-08-01), Fang
patent: 5701602 (1997-12-01), Shimoda

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