Method and apparatus for reducing power consumption in memory ci

Details Method and apparatus for reducing power consumption in memory ci Method and apparatus for reducing power consumption in memory ci

1995-01-27

1996-06-25

Nguyen, Tan T.

Static information storage and retrieval

Powering

Conservation of power

36518905, 365233, 3652335, G11C 700

Patent

active

055306764

ABSTRACT:
A clock signal (202) is received, wherein the rising edge of the clock signal (202) controls an operation of a memory cell (224) of a memory circuit (200). Address information (204) is received and predecoded prior to the rising edge of the clock signal (202) to produce a row select signal (210). A control signal (201), which is received prior to the rising edge of the clock signal, determines whether the operation is a read operation or a write operation. If the operation is a write operation, new data information (218) is received a data delay after the rising edge of the clock signal (202); the row select signal (210) is delayed such that the memory cell (224) is selected at least a data delay after the rising edge of the clock signal (202); and the new data information (218) is written to the memory cell (224).

REFERENCES:
patent: 4404654 (1983-09-01), Kamuro et al.
patent: 4813021 (1989-03-01), Kai et al.

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