Boots – shoes – and leggings
Patent
1995-05-05
1997-05-13
Harvey, Jack B.
Boots, shoes, and leggings
395306, 364707, G06F 132
Patent
active
056301456
ABSTRACT:
A power conservation computer architecture is provided for disabling a clock signal to all peripheral devices and bus controllers located on a plurality of Peripheral Component Interconnect (PCI) buses when it is determined that all of the PCI buses are idle. The PCI buses are determined to be idle through the use of a Power Management Unit (PMU) controller connected to the first of the plurality of PCI buses. The PMU controller first determines and stores in memory a time constant corresponding to the amount of time required for the PMU controller to read the head configuration of the farthest peripheral device from the PMU controller when there is no activity on any of the buses. Then, during the operation of the computer architecture, if the first PCI bus is determined to be idle, a comparison is made between the time constant and a measurement of the length of time required to read the head configuration of the farthest peripheral device from the PMU controller. If the time to access the head configuration is less than the time constant plus a predetermined time constant, thereby indicating that there is no activity on any of the PCI buses, a clock signal from the PMU controller is stopped, thus placing the bus controllers and peripheral devices in a reduced power consumption state. The clock signal to the bus controllers and peripheral devices is resumed by the PMU controller when an asynchronous signal is sent from the peripheral devices or bus controllers to the PMU controller to indicate that data exchange on the PCI buses will be occurring.
REFERENCES:
patent: 5029272 (1991-07-01), Fourcroy et al.
patent: 5113518 (1992-05-01), Durst, Jr. et al.
patent: 5167024 (1992-11-01), Smith et al.
patent: 5396602 (1995-03-01), Amini et al.
patent: 5396635 (1995-03-01), Fung
Harvey Jack B.
Lefkowitz Sumati
United Microelectronics Corp.
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