Method and apparatus for reducing parasitic capacitance

Details Method and apparatus for reducing parasitic capacitance Method and apparatus for reducing parasitic capacitance

2005-03-31

2009-11-17

Lee, Eugene (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S516000, C257S535000, C257S306000, C257SE27034

Reexamination Certificate

active

07619298

ABSTRACT:
A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.

REFERENCES:
patent: 5059548 (1991-10-01), Kim
patent: 5162248 (1992-11-01), Dennison et al.
patent: 6252293 (2001-06-01), Seyyedy et al.
patent: 6288604 (2001-09-01), Shih et al.
patent: 6933551 (2005-08-01), Stribley et al.
patent: 7130182 (2006-10-01), Balster et al.
U.S. Appl. No. 10/839,932, filed May 5, 2004, Abughazaleh.

Affiliated with

Also associated with

Rating

Method and apparatus for reducing parasitic capacitance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for reducing parasitic capacitance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing parasitic capacitance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4057448