Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
1998-11-20
2001-08-28
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S534000
Reexamination Certificate
active
06281737
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to silicon-on-insulator field effect transistors, and more particularly to reduction of parasitic bipolar current in such FET's.
BACKGROUND OF INVENTION
Silicon-on-insulator (“SOI”) field effect transistors (“FET's”), particularly wide SOI FET's in pass gate applications, suffer a parasitic bipolar currents the effects of which are most severe when the circuit is initially turned on after being idle for a long period of time, i.e. a time in the range of milliseconds. This is because the floating body of the SOI FET can develop a body charge over time. The amount of such body charge will depend on the potentials at the source, drain, and gate terminal electrodes of the SOI FET. The maximum amount of charging occurs when the gate is completely turned off and both the source and drain electrode are biased at the highest potential vdd. During the subsequent switching of the source or drain electrode of the SOI FET, the accumulated body charge will be discharged by means of a transient bipolar current. This parasitic current degrades performance, including noise and timing performance. See, for example, C. Chuang, P.Lu, and C. Anderson,
SOI for Digital CMOS VLSI: Design Considerations and Advances
, Proceedinigs of the IEEE, v. 86, No. 4, April 1998, p. 689-720, which is hereby incorporated by reference (discussing the nature of and occasion for the parasitic current in connection with the description therein of FIGS.
1
and
2
), and C. I-Isieh et al.,
Methods to Enhance SOI SRAM Cell Stability
, U.S. Pat. No. 5,774,411, which is hereby incorporated by reference (discussing, in the Background of the Invention section, the parasitic, lateral, bipolar transistor formed by the source, drain and channel, i.e., floating body, region of an FET). Pass gates are particularly susceptible to parasitic bipolar current because it is not uncommon in pass gate applications for both the source and drain of a pass gate to be driven to a relatively high voltage level, and because it is not uncommon for pass gates to be relatively wide.
A number of circuit structures are known for mitigating this problem in a variety of contexts. For example, for a number of applications, including pass gates, it is known to connect the SOI NFET body to the NFET gate. Id. at p. 706. This has the beneficial effect of minimizing Vt loss (aka “dynamic Vt control”), improving drive, and suppressing leakage, but is disadvantageous from the standpoint of area increase and incompatibility with bulk design.
It is also known to actively bias the body of SOI NFET and PFET devices in an inverting output stage of a driver. Id. at 709 (showing a network of FET's responsive to the input to and output from the SOI output stage). Such an arrangement also has the beneficial effect of minimizing Vt loss, improving drive. and suppressing leakage, but has disadvantages of more expensive fabrication process, significantly larger area for the extra diode and capacitor, and increasing input capacitance (which slows down the circuit). It is also known to discharge the body of a SOI FET responsive to a signal timed to occur shortly before the gate of the FET is selected (hereinafter, a “pre-discharge signal”), or responsive to the accumulated charge on the body. This discharging has the possible benefit of reducing parasitic bipolar current during functional, initial cycle switching, provided that the discharging is early enough or that the discharge device is large enough with respect to the charge on the body to sufficiently discharge the body during the discharging interval before the gate is selected. In addition to these limitations, it also disadvantageously requires that a timing signal be generated for the pre-discharge signal.
Therefore, although there are known circuits and techniques for mitigating parasitic, bipolar current in an insulated body FET, because of the disadvantages described above, and others, a need remains for improved methods and structures for mitigating such parasitic, bipolar current.
SUMMARY OF THE INVENTION
In a first form, an apparatus for reducing parasitic bipolar current in a field effect transistor (“FET”) includes an insulated body NFET, having a body disposed, at least in part, below a gate electrode of the insulated body NFET. Body-charge control circuitry is coupled to the gate of the NFET and to the body. The body-charge control circuitry includes a body-charge control FET, with first and second conducting electrodes and a gate electrode, has its first conducting electrode electrically coupled to the body of the insulated body NFET and its second conducting electrode electrically coupled to an electrical sink. The body-charge control circuitry also includes an inverter, having its input electrically coupled to the insulated body NFET gate, and its output electrically coupled to the body-charge control NFFT gate, so that when a voltage applied to the insulated body NFET gate is above a certain first voltage level, the inverter output voltage tends to turn off the body-charge control FET and electrically isolate the body from the sink, thereby permitting a charge to accumulate on the body. Conversely, when the voltage applied to the insulated body NFET gate electrode is below a certain second voltage level, the inverter output voltage tends to turn on the body-charge control FET and electrically couple the body to the sink, thereby discharging at least a portion of any charge accumulated on the body.
In an additional aspect, the apparatus includes a SOI PFET. If the SOI PFET is susceptible to parasitic bipolar current the apparatus includes a second body-charge control circuitry, for the PFET. The second body-charge control circuitry isolates the PFET body when the PFET is on, and discharges the body when the PFET is off. (Note that in the case of an insulated body PFET, the term “discharge” is herein used differently than in the case of an insulated body NFET. For the PFET, negative charge may accumulate on the insulated body when the body is isolated; whereas for the NFET positive charge may accumulate when the NFET body is isolated. Therefore, for the PFET, negative charge is discharged. But for the NFET, positive charge is discharged.)
In another form, a method includes steps for reducing parasitic bipolar current in a NFET having an insulated body, the body being disposed, at least in part, below a gate electrode of the NFET. In one step, the body of the insulated body NFET is electrically isolated, responsive to a voltage applied to the insulated body NFET gate electrode being above a certain first voltage level. This permits a charge to accumulate on the body, lowering the threshold voltage for the insulated body NFET.
In another step, at least a portion of the charge on the body of the insulated body NFET is electrically discharged, responsive to the voltage applied to the insulated body NFET gate electrode being below a certain second voltage level. This discharging reduces parasitic bipolar current which would otherwise occur upon turning the NFET back on if the body had charged up during the time when the NFET was off.
In another aspect, the discharging includes electrically coupling the insulated NFET body to a sink having a voltage lower than a voltage level of the accumulated charge. Furthermore, the SOI FET body is thus coupled to the sink whenever the SOI FET gate electrode voltage is below the certain second voltage level.
In another form, a method includes steps for reducing parasitic bipolar current in a PFET having an insulated body, the body being disposed, at least in part, below a gate electrode of the PFET. The body of the insulated body PFET is discharged, responsive to a voltage applied to the insulated body PFET gate electrode being above a certain first voltage level. Also, the body of the insulated body PFET is electrically isolated, responsive to the voltage applied to the insulated body PFET gate electrode being below a certain second voltage level. The discharging of the PFET body while the P
Kuang Jente Benedict
Lu Pong-Fei
Saccamango Mary Joseph
Cunningham Terry D.
England Anthony V. S.
International Business Machines - Corporation
McBurney Mark E.
Tra Quan
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