Television – Image signal processing circuitry specific to television – With details of static storage device
Reexamination Certificate
1999-07-22
2003-07-01
Miller, John (Department: 2714)
Television
Image signal processing circuitry specific to television
With details of static storage device
C348S715000, C348S714000, C348S206000, C345S543000, C345S545000, C345S547000
Reexamination Certificate
active
06587158
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to video processing and, more particularly, to techniques for vertical processing of horizontally scanned video images.
2. Description of the Related Art
FIG. 1
shows an illustration of a rectangular picture area
10
with a horizontal full row scanning sequence. The rectangular picture area
10
is divided into a number of rows of data
12
which are scanned from left to right, with rows being traversed from the top of the image to the bottom. Video data is generally produced in this type of horizontal raster-scanned format. Video data is also provided in this fashion from a wide variety of data sources (e.g., broadcast, video tape, video disc) and used in the same sequence for display purposes (e.g., television, computer monitors, LCD displays).
FIG. 2
is a diagram of a prior art video processor
14
, which processes video data before displaying or storing the data. The video processor
14
typically receives data
16
in a raster-scan format. The video processor
14
must deliver the processed video data
18
in the same or similar format. Examples of common types of processing include image size reduction/enlargement (or “scaling”), filtering to remove high frequencies, filtering to enhance detail in the image, or format conversion from one video data type to another (e.g., deinterlacing).
Many types of processing only utilize data from horizontally adjacent pixel locations. This naturally fits with the existing data ordering of the raster-scanned format and is relatively economical to implement. In addition, the row ordering of the video data naturally aligns with the current dynamic random access memory (DRAM) row/column chip organization which provides significantly reduced access times for in-row (or horizontal) accesses.
However, when video data must be processed in the vertical direction, particularly when multiple vertically adjacent pixel locations are simultaneously needed for processing, the raster-scanned format no longer provides the data needed in the correct or appropriate order.
FIG. 3
is a diagram of a horizontal raster-scanned video image
20
divided into a number of scan lines
22
and pixels
24
. In order to vertically process the data, multiple pixels are needed which come from different scan lines
22
.
Since the pixel data is presented in a horizontally ordered sequence, multiple lines of video data must be available in order to have simultaneous access to multiple vertically aligned pixels. This requires storing or buffering of those multiple lines in order to make the data available for processing. In the past, this has either not been done at all due to implementation cost reasons, or has been done by using multiple on-chip line memories to store a number of horizontal lines of pixel data. If nothing is done, the result is nonexistent or poor quality processing due to lack of vertical pixel data being available.
The main problem with using on-chip line memories for vertical processing of horizontal raster-scanned video is that they are extremely large, thus requiring a significant increase in die area (and therefore chip cost). This is particularly true if a large number of line memories are needed for high-quality processing. A single line memory for the ITU-R BT.601 standard digital video formats typically contains 720 16-bit pixels, or 11520 memory bits.
Because multiple line memories are needed for quality vertical processing, and since some video processing implementations require multiple serial processing stages, each with its own set of line memories, the required amount of on-chip memory can be very large in many different scenarios. For instance, with 6 line memories per processing stage, and with 3 serial processing stages the number of required memory bits would be over 200 kbits.
External memories have not been often utilized due to the fact that accessing vertically adjacent data results in the crossing of DRAM row (or page) boundaries, with the attendant severe reduction in available memory bandwidth. The implementation cost issue is compounded by the fact that high quality processing typically requires more data, i.e., better vertical processing requires a larger number of simultaneously available vertically aligned pixels.
On-chip memory requirements of this order significantly reduce the available implementation options (e.g., prototyping with field programmable gate arrays (FPGA) or most gate-arrays is not viable) and increase the chip die area and cost. While these expensive line memories for vertical video processing cannot be eliminated completely, any reduction of the memory requirements would be valuable.
In view of the foregoing, it is desirable to have a method that provides for high quality vertical processing of horizontally scanned video while minimizing cost and reducing the number of full line memories required.
SUMMARY OF THE INVENTION
The present invention fills these needs by providing an efficient and economical method and apparatus for high quality vertical video processing utilizing off-chip commodity memory and an alternative scan sequence for vertical processing. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
In one embodiment of the present invention, a digital image processor is provided. The digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.
In another embodiment of the present invention, a method of processing image data is provided. The method includes buffering a block of raster-scanned data in an input buffer. Vertical slices of the raster-scanned data are sequentially retrieved and processed, forming processed vertical slices. The processed vertical slices are then stored in an output buffer to form a processed block of raster-scanned data. The vertical slices are preferably comprised of a slice core and at least one pair of wings, which overlap the slice core of horizontally adjacent vertical slices. The width of the processed block of raster-scanned data is preferably equal to the width of the slice core.
An advantage of the present invention is that the on-chip memory requirements for high quality vertical processing are significantly reduced. By dividing the rectangular video field or frame into smaller portions, the memory requirements of the system can be reduced by an order of magnitude. Therefore, the image processing chip is not limited by the constraints of having only a small number of on-chip line memories. In addition, by not having to use the line memories, costs are dramatically reduced.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
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p
Adams Dale R.
Banks Jano D.
Thompson Laurence A.
DVDO, Inc.
Lo Linus H.
Miller John
Perkins Coie LLP
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