Method and apparatus for reducing noise in integrated circuit ch

Details Method and apparatus for reducing noise in integrated circuit ch Method and apparatus for reducing noise in integrated circuit ch

1998-08-28

2000-05-09

Sherry, Michael J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, 257533, 257659, H02H 322

Patent

active

060612223

ABSTRACT:
A method and apparatus for reducing noise in integrated circuit chips (ICs). The apparatus comprises on-die capacitance in conjunction with one or more resistive loss elements, which provide an AC termination for on-die power events. The on-die capacitance can be instantiated in metal layers alone, in gate oxides or in gate oxides combined with metal structures. The capacitance may be provided by the capacitive characteristics of adjacent metal layers of the power distribution structure of the IC. When the capacitance is provided in this manner, the resistive loss element corresponds to the linear resistance of thin lines on the metal layers of the power distribution structure. The resistive loss element may, alternatively, be comprised of a field effect transistor (FET) or a metal oxide semiconductor field effect transistor (MOSFET). By utilizing on-die capacitance in conjunction with one or more resistive loss elements, the IC is provided with loss characteristics and power filter characteristics that are effective in reducing power noise and EMI. The method ensures that the values of the resistive loss element and of the capacitance element are selected for optimum reduction of power noise without causing on-die resonance.

REFERENCES:
patent: 4890187 (1989-12-01), Tailliet et al.
patent: 5721656 (1998-02-01), Wu et al.
patent: 5923076 (1999-07-01), Campardo et al.

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