Boots – shoes – and leggings
Patent
1989-01-27
1993-02-09
Fleming, Michael R.
Boots, shoes, and leggings
364228, 3642434, 36424341, 3642283, 364DIG1, 36518901, G06F 1516, G06F 1300
Patent
active
051858754
ABSTRACT:
Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently writes the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently writes the portion of the transferred data that is most current in the SCU memory and reads the written data that is most current in the SCU memory and reads the written data for transfer to the requesting CPU.
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Chinnaswamy Kumar
Gagliardo Michael A.
Lynch John J.
Tessari James E.
Digital Equipment Corporation
Fleming Michael R.
Ray Gopal C.
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