Method and apparatus for reducing lock time in dual...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S159000, C375S376000

Reexamination Certificate

active

06937075

ABSTRACT:
A phase-locked loop includes a phase detector to measure a phase offset between a reference clock signal and a feedback clock signal, and to generate first and second output control signals having a pulse width corresponding to the phase offset. The phase locked loop further includes a first pulse width control circuit coupled to the phase detector to reduce the pulse width of the first output control signal producing a first modified output control signal, a second pulse width control circuit coupled to the phase detector to reduce the pulse width of the second output control signal producing a second modified output control signal, a first charge pump coupled to the phase detector to provide a first charge signal responsive to the first and second output control signals, and a second charge pump coupled to the first and second pulse width control circuits to provide a second charge signal responsive to the first and second modified output control signals.

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