Method and apparatus for reducing leakage currents in an I/O buf

Details Method and apparatus for reducing leakage currents in an I/O buf Method and apparatus for reducing leakage currents in an I/O buf

1996-03-25

1999-04-06

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

327170, 327377, 327437, 327540, 326 83, 326 86, H03K 300

Patent

active

058923772

ABSTRACT:
A method and apparatus for reducing leakage currents in a high voltage tolerant I/O buffer. An I/O buffer designed to tolerate high external voltages by blocking such voltages at a passgate in a p-output path that uses a device between a p-driver gate node and a p-gate node of the passgate to ensure that the p-transistor of the passgate is turned on when the p-driver is driving the pad high. A second device isolates the p-gate node of the passgate from the pad until a pad voltage reaches a predetermined level. Once the pad voltage reaches the predetermined level, the device drives the voltage at the p-gate node of the passgate to that of the pad. Maintaining the p-transistor of the passgate on while the p-driver is driving the pad high allows a rapid hard shut-off of the p-driver as the I/O buffer tri-states the pad. Additionally, the second device maintains the necessary voltage protection by insuring a hard shut-off of the p-transistor of the passgate when the voltage at the pad reaches a predetermined level.

REFERENCES:
patent: 5315187 (1994-05-01), Cheng
patent: 5381059 (1995-01-01), Douglas
patent: 5444397 (1995-08-01), Wong et al.
patent: 5512844 (1996-04-01), Nakakura et al.
patent: 5576635 (1996-11-01), Partovi et al.

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