Method and apparatus for reducing jitter in a phase locked loop

Details Method and apparatus for reducing jitter in a phase locked loop Method and apparatus for reducing jitter in a phase locked loop

1994-08-31

1996-02-13

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327156, 331 14, 331 17, 331 25, 331DIG2, 375376, H03L 706

Patent

active

054914396

ABSTRACT:
A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.

REFERENCES:
patent: 4074205 (1978-02-01), Robe
patent: 4271434 (1981-06-01), Sakamoto
patent: 4276512 (1981-06-01), Wittke
patent: 4322643 (1982-03-01), Preslar
patent: 4577121 (1986-03-01), Sano et al.
patent: 4580107 (1986-04-01), Caldwell et al.
patent: 4628461 (1986-12-01), Adams
patent: 4633193 (1986-12-01), Scordo
patent: 4668918 (1987-05-01), Adams
patent: 4748346 (1988-05-01), Emori
patent: 4754225 (1988-06-01), Minuhin
patent: 4847519 (1989-07-01), Wahl et al.
patent: 4875108 (1989-10-01), Minuhin et al.
patent: 4876519 (1989-10-01), Davis et al.
patent: 4893094 (1990-01-01), Herold et al.
patent: 4942370 (1990-07-01), Shigemori
patent: 4959618 (1990-09-01), Shier
patent: 5015970 (1991-05-01), Williams et al.
patent: 5029282 (1991-07-01), Ito
patent: 5065115 (1991-11-01), Pletz-Kirsch et al.
patent: 5068625 (1991-11-01), Baker et al.
patent: 5072134 (1991-12-01), Min
patent: 5081427 (1992-01-01), Suarez
patent: 5095287 (1992-03-01), Irwin et al.
patent: 5095288 (1992-03-01), Dent
patent: 5126690 (1992-06-01), Bui et al.
patent: 5128632 (1992-07-01), Erhart et al.
patent: 5142247 (1992-08-01), Lada, Jr et al.
patent: 5166641 (1992-11-01), Davis et al.
patent: 5180928 (1993-01-01), Choi
patent: 5180993 (1993-01-01), Dent
patent: 5206550 (1993-04-01), Mehta
patent: 5208546 (1993-05-01), Nagaraj et al.
patent: 5220294 (1993-06-01), Ichikawa
patent: 5233314 (1993-08-01), McDermott et al.
patent: 5233314 (1993-08-01), McDermott et al.
patent: 5241700 (1993-08-01), Geesen et al.
patent: 5257286 (1993-10-01), Ray
patent: 5285173 (1994-02-01), Reynolds
patent: 5304952 (1994-04-01), Quiet et al.
patent: 5304955 (1994-04-01), Atriss et al.
patent: 5304957 (1994-04-01), Edwards
patent: 5315270 (1994-05-01), Leonowich
patent: 5319320 (1994-06-01), Abe et al.
patent: 5332978 (1994-07-01), Yabuki et al.
patent: 5334951 (1994-08-01), Hogeboom
patent: 5399995 (1995-03-01), Kardontchik et al.

Affiliated with

Also associated with

Rating

Method and apparatus for reducing jitter in a phase locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for reducing jitter in a phase locked loop , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing jitter in a phase locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-242883