Method and apparatus for reducing jitter and improving testabili

Details Method and apparatus for reducing jitter and improving testabili Method and apparatus for reducing jitter and improving testabili

1995-02-23

1996-04-23

Lee, Benny

Oscillators

With frequency calibration or testing

331179, 331158, 324548, 341120, H03M 110, H03B 500

Patent

active

055111262

ABSTRACT:
An oscillator such as a pulled-crystal oscillator (50) provides low clock jitter by converting a sinusoidal voltage on a crystal's (51) terminals into a digital square wave with a comparator (56). The oscillating frequency of the crystal (51) is pulled by selectively switching in extra capacitance through capacitor digital-to-analog converters (CDACs) (57, 58). The oscillator (50) has built-in testability which allows individual capacitors in the CDACs (57, 58) to be quickly tested for opens. A scan path is connected to the inputs of the CDACs (57, 58) for selecting individual capacitors. A first input terminal of the comparator (56) is precharged before a capacitor under test (171) is connected. A comparison voltage is provided to the second input terminal. The capacitor under test (171) is determined to be functional if, after being connected to the first input terminal of the comparator (56), it discharges the first input terminal to a voltage below the comparison voltage, causing the comparator (56) to switch.

REFERENCES:
patent: 3824459 (1974-07-01), Uchida
patent: 4093915 (1978-06-01), Briefer
patent: 4782309 (1988-11-01), Benjaminson
patent: 5029268 (1991-07-01), Pfandler
patent: 5036294 (1991-07-01), McCaslin
patent: 5063359 (1991-11-01), Leonowich
patent: 5117206 (1992-05-01), Imamura
patent: 5151666 (1992-09-01), Tamagawa
patent: 5175547 (1994-12-01), Lyon et al.
Takehiko Uno and Yoshio Shimoda; "A New Digital TCXO Circuit Using a Capacitor-Switch Array"; 37th Annual Frequency Control Symposium; IEEE 1983; pp. 434-441 (1983).

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