Patent
1995-03-15
1997-12-09
Treat, William M.
395800, G06F 900
Patent
active
056969589
ABSTRACT:
A pipeline processor, when processing a branch instruction, initiates fetching of both the target and fall-through streams prior to execution of the branch instruction such that the number of pipeline cycles between completion of execution of the branch instruction and initiation of processing of the head instruction of the target or fall-through stream is less than the minimum number of pipeline cycles between fetching of an instruction and the execution of the instruction. At least one otherwise wasted pipeline cycle is saved by early instruction fetching and storing in a prefetch register. In some cases, two or more otherwise wasted cycles can be saved.
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Killian Earl A.
Mowry Todd C.
Maung Zarni
Silicon Graphics Inc.
Treat William M.
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