Method and apparatus for reducing delay in a bus provided...

Coded data generation or conversion – Digital code to digital code converters – Data rate conversion

Reexamination Certificate

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C341S050000

Reexamination Certificate

active

07400276

ABSTRACT:
A mechanism for use with a bus provided from parallel, capacitively-coupled bus lines to restrict a number of possible transitions on the bus to a number that is smaller than the maximum number of possible transitions so that data transmissions on the bus occur at a transmission rate which is higher than the transmission rate allowable if the number of transitions had not been restricted.

REFERENCES:
patent: 3639900 (1972-02-01), Hinz, Jr.
patent: 5412689 (1995-05-01), Chan et al.
patent: 5535187 (1996-07-01), Melas et al.
patent: 5646556 (1997-07-01), Longwell et al.
patent: 5880981 (1999-03-01), Kojima et al.
patent: 5994946 (1999-11-01), Zhang
patent: 6046943 (2000-04-01), Walker
patent: 6140850 (2000-10-01), Inoue
patent: 6289490 (2001-09-01), Boyd et al.
patent: 6442628 (2002-08-01), Bastiani et al.
patent: 6580538 (2003-06-01), Kartalopoulos
patent: 6832277 (2004-12-01), Durham et al.
patent: 7116126 (2006-10-01), Tomsio et al.
Ramprasad, S.; Shanbhag, N.R.; Hajj, I.N. “Information-theoretic bounds on average signal transition activity [VLSI systems]”. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. vol. 7, Issue 3, Sep. 1999 pp. 359-368.
Benini, L.; De Micheli, G.; Macii, E.; Poncino, M.; Quer, S. “Power optimization of core-based systems by address bus encoding”. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. vol. 6, Issue 4, Dec. 1998 pp. 554-562.
Youngsoo Shin; Soo-Ik Chae; Kiyoung Choi. “Reduction of bus transitions with partial bus-invert coding”. Electronics Letters. vol. 34, Issue 7, Apr. 2, 1998 pp. 642-643.
Youngsoo Shin; Soo-Ik Chae; Kiyoung Choi. “Partial bus-invert coding for power optimization of system level bus”. Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on. Aug. 10-12, 1998 pp. 127-129.
Hirose, K.; Yasuura, H. “A bus delay reduction technique considering crosstalk”. Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings. Mar. 27-30, 2000 pp. 441-445.
Victor, B. and Keutzer, K. “Bus encoding to prevent crosstalk delay”. Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on. Nov. 4-8, 2001 pp. 57-63.
Victor et al. “Bus encoding to prevent crosstalk delay”. IEEE/ACM International Conference on Computer Aided Design, 2001. Nov. 4-8, 2001 pp. 57-63.
Anders et al.; “A Transition-Encoded Dynamic Bus Technique for High-Performance Interconnects;” 2002 Sumposium on VLSE Circuits Digest of Technical Papers; 0-7803-7310-3; 202 IEEE; pp. 16 and 17.
Sotiriadis et al.; “Transition Pattern Coding: An Approach to Reduce Energy in Interconnect;” date unknown.
Sotiriadis et al.; “Reducing Bus Delay in Sub-Micron Technology Using Coding:” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2001; pp. 109-114.
Sotiriadis et al.; “Bus Energy Reduction by Transition Pattern Coding Using a Detailed Deep Submicrometer Bus Model:” IEEE Transactions on Circuits and Systems •|: Fundamental Theory and Applications, vol. 50, No. 10, Oct. 2003: pp. 1280-1295.
Sotiriadis et al.: “Bus Enengy Minimization by Transition Pattern Coding (TPC) In Deep Sub-Micron Technologies;” IEEE/ACM International Converence on CAD (ICCAD), San Jose, 2000, pp. 322-327.
Sotiriadis et al.; “Transition Pattern Coding: An Approach to Reduce Energy in Interconnect;” 26th European Solid-State Circuit Conference (ESSERC); Stockholm, 2000, pp. 320-323.
Sotiriadis et al.; “Low Power Bus Coding Techniques Considering Inter-wire Capacitances;” IEEE Custom Integrated Circuits Conference 2000: pp. 507-510.
Paul Peter P. Sotiriadis, “Interconnect Modeling and Optimization In Deep Sub-Micron Technologies”, Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Doctor of Philosophy at the Massachusetts Institute of Technology, May 2002, 233 pages.

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