Method and apparatus for reducing data delay within a multi-chan

Details Method and apparatus for reducing data delay within a multi-chan Method and apparatus for reducing data delay within a multi-chan

1995-10-02

1998-08-04

Gaffin, Jeffrey A.

Coded data generation or conversion

Analog to or from digital conversion

Multiplex

341123, H04L 700

Patent

active

057900728

ABSTRACT:
A multi-channel integrated circuit, which includes N processing channels and a functional circuit which is time-shared between each of the N channels for processing data in accordance with a first clock strobe. Also included is a time-division multiplexed bus for providing synchronized data to and receiving synchronized data from said circuit in accordance with a second clock strobe. The data are thereby processed within said shared circuit in synchronization with said first and second clock strobes.

REFERENCES:
patent: 3571516 (1971-03-01), Ohyama et al.
patent: 4881191 (1989-11-01), Morton
patent: 5262970 (1993-11-01), Sevenhans et al.
patent: 5592480 (1997-01-01), Carney et al.

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