Method and apparatus for reducing checking costs in fault tolera

Details Method and apparatus for reducing checking costs in fault tolera Method and apparatus for reducing checking costs in fault tolera

1992-12-30

1994-08-16

Canney, Vincent P.

Excavating

371 91, 371 683, G06F 1116

Patent

active

053394089

ABSTRACT:
According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

REFERENCES:
patent: 4604750 (1986-08-01), Manton et al.
patent: 4907228 (1990-03-01), Bruckert et al.
patent: 5068780 (1991-11-01), Bruckert et al.
patent: 5249187 (1993-09-01), Bruckert et al.
patent: 5255367 (1994-03-01), Bruckert et al.
patent: 5291494 (1993-10-01), Bruckert et al.
Patent application Ser. No. 07/388,327, PD89-0174, "Memory for a Digital Data Processing System Including Circuit for Controlling Refresh Operations During Power-Up and Power-Down Conditions".
Patent application Ser. No. 07/093,572, PD88-0068, "Dual-Zone, Fault Tolerant Computer System with Error Checking on I/O W Rites".
Patent application Ser. No. 07/093,179, PD88-0071, "Fault Tolerant Computer System with Fault Isolation and Repair".
Patent application Ser. No. 07/095,096, PD88-0072, "Synchronized Twin Computer System".
New Patent Application Filed Dec. 30, 1992, PD92-0537, "A Method and Apparatus for Preservation of System Information in a Fault Tolerant System".
New Patent Application Filed Dec. 30, 1992, PD92-0539, "DMA Controller for Memory Scrubbing".
New Patent Application Filed Dec. 30, 1992, PD92-0540, "Apparatus and Method of Data Transfer Between Systems Using Different Clocks".
New Patent Application Filed Dec. 30, 1992, PD92-0542, "An Improved Phase Detector Apparatus".

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