Method and apparatus for reducing capacitive coupling...

Details Method and apparatus for reducing capacitive coupling... Method and apparatus for reducing capacitive coupling...

2007-04-03

2007-04-03

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S773000, C438S622000

Reexamination Certificate

active

10001707

ABSTRACT:
An integrated circuit (78) includes a memory circuit (10, 110, 210, 310, 410) having a group of bitlines (21–28, 121–128, 221–228, 321–328, 421–428), and having an array of memory cells (11–18) which are each electrically coupled to two bitlines of the group. Each bitline has alternating first (61, 63, 65) and second (62, 64, 66) portions that are respectively located in metalization layers disposed on opposite sides of an insulating layer (84). The first and second portions are electrically coupled by vias (51–54, 334, 437) which extend through the insulating layer. Along the length of each bitline, each first and second portion thereof is disposed in a metalization layer opposite from the metalization layer containing the adjacent portion of each adjacent bitline.

REFERENCES:
patent: 5841688 (1998-11-01), Sukegawa et al.
Takeda, et al. “A 16-mb 400-MHz Loadless CMOS Four-Transistor SRAM Macro”, IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1631-1640.

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