Cleaning and liquid contact with solids – Processes – Including work heating or contact with combustion products
Reexamination Certificate
2001-10-10
2004-10-19
Markoff, Alexander (Department: 1746)
Cleaning and liquid contact with solids
Processes
Including work heating or contact with combustion products
C134S001100, C134S030000
Reexamination Certificate
active
06805752
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to shallow trench isolation (STI) etching apparatus and methods and more particularly to reducing acid contaminated residue associated therewith.
BACKGROUND OF THE INVENTION
In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power as well as compromise functionality. Among some examples of reduced functionality include latch-up, which can damage the circuit temporarily or permanently, noise margin degradation, voltage shift and cross-talk.
Shallow trench isolation (STI), is the preferred electrical isolation technique especially for a semiconductor chip with high integration. In general, conventional methods of producing an STI feature include forming a hard mask over the trench layer, patterning a photoresist etching mask over the hard mask, etching the hard mask through the photoresist etching mask to form a patterned hard mask, and thereafter etching the trench layer to form the STI feature. Subsequently, the photoresist etching mask is removed and the STI feature is back-filled with a dielectric material.
Frequently STI features are etched with a sequential process flow, where the mask layers are etched in one chamber and the silicon trench is etched in another chamber. Etching is frequently performed by way of a plasma. Typically, in a plasma etching process an etchant source gas supplied to an etching chamber where the plasma is ignited to generate ions from the etchant source gas. Ions are then accelerated towards the process wafer substrate, frequently by a voltage bias, where they remove material (etch) from the process wafer. Various gas chemistries are used to provide variable etching rates for different etching target materials. Frequently used etchant sources include chloro and fluoro-hydrocarbons in addition to HBr to etch through for example, a silicon layer to form a shallow trench isolation feature. Another etchant chemistry, for etching through silicon, for example, includes a Cl
2
/O
2
/HBr-based chemistry. During and after the etching process halogen species such as chlorine and bromine remain on the target surface where, for example, they are incorporated into the sidewalls and bottoms of etched features as well as into overlying layers of photoresist. Since hydrogen is also present in and around the halogen species, highly corrosive acids may condense and form on the process wafer causing corrosive damage. HBr, for instance, is a highly corrosive acid that is frequently formed on the surface of the process wafer.
FIG. 1
shows a typical process chamber configuration used in STI etching. The typical process chamber, for example, includes several different etching chambers,
10
,
12
,
14
, and
16
, in addition to a wafer orientation chamber
18
, a cool down chamber
24
and loadlock chambers
20
and
22
. The robotic arm transfer mechanism is centrally located at
26
. In a typical process in STI etching, as explained, several different etching steps with different etching chemistries may be involved thus having the process wafer transferred by robotic arm
26
between multiple etching chambers, for example
10
,
12
,
14
, and
16
. Following etching, the process wafer may be transferred by robotic arm
26
to cool down chamber
24
to cool the process wafer prior to transfer to a loadlock chamber, for example,
20
or
22
where the chamber is pressurized to atmospheric pressure for unloading.
During this process, corrosive acids, such as HBr may condense onto the process wafer surface which also contains for example, loose particles from the etching process. Further, during the pressurization process the particles may become dislodged and adhere to the chamber walls and robotic arm thereby causing corrosive damage to the chamber and robotic arm as well as to the process wafer. As a result, over time, the loadlock chambers accumulate residual corrosive particles which can cause damage to process wafers as they are moved through the loadlock chamber thereby necessitating frequent equipment shutdown for cleaning. Another shortcoming of the prior art procedure and apparatus for STI etching may be potential adverse health consequences to equipment operators from an undesired buildup of such contamination.
There is therefore a need in the semiconductor processing art to develop apparatus and methods whereby the level of acid (e.g., HBr) contaminated particles on process wafers and STI etching apparatus in an STI etching procedure is reduced thereby minimizing damage to both process wafers and STI etching apparatus as well as reducing the potential effect of adverse health consequences.
It is therefore an object of the invention to provide a method and apparatus whereby the level of acid (e.g., HBr) contaminated particles is reduced in an STI etching process while overcoming other shortcomings and deficiencies in the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method and apparatus for reducing acidic contamination on a process wafer following a plasma etching process.
In a first embodiment of the present invention, a method is provided for reducing acidic contamination on a process wafer following a plasma etching process including providing an ambient controlled heating chamber for accepting transfer of a process wafer under controlled ambient conditions; transferring the process wafer to the heating chamber under controlled ambient conditions following plasma etching of the process wafer; providing a heat exchange surface within the heating chamber for mounting the process wafer in heat exchange relationship thereto; mounting the process wafer on a heat exchange surface contained within the heating chamber; and, heating the process wafer to a temperature sufficient to vaporize an acidic residue thereon to form acidic vapors; and, removing the acidic vapors from the heating chamber.
In another embodiment, the step of removing the acidic vapors is carried cut simultaneously with the step of heating the process wafer. In another related embodiment, the steps of heating the process wafer and removing the acidic vapor are carried out for a period of time sufficient to remove from about 50 percent to about 100 percent of the acidic residue. In yet another related embodiment, the step of transferring the process wafer to the heating chamber is carried out prior to transferring the process wafer to an unloading chamber for unloading the process wafer.
In yet further related embodiments, the process wafer is heated within a temperature range of about 75° C. to about 100° C. Further, the ambient pressure within the heating chamber is maintained within a range of 10 milliTorr to 500 milliTorr. Yet further, the step of heating the process wafer is carried out for a period of about 30 to about 90 seconds.
In further related embodiments, the heat exchange surface is supplied with a heat exchange fluid. Further, the heat exchange fluid is supplied in fluid communication with a heat exchanger. Yet further, the heat exchanger is provided with means for sensing a fluid flow rate and means for sensing a temperature. Further yet, at least one of the fluid flow rate and the temperature is controllably selected by a computer.
In another related embodiment, the step of transferring the process wafer to the heating chamber is effectuated by a means
Chang Chih-Yung
Chien Shiou Fieng-Chang
Liu Hsiang-Hsing
Markoff Alexander
Taiwan SEmiconductor Manufacturing Co., Ltd
Tung & Associates
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