Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2000-03-31
2004-06-01
Chin, Stephen (Department: 2634)
Pulse or digital communications
Equalizers
Automatic
C375S348000, C375S229000, C375S233000
Reexamination Certificate
active
06744814
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to equalization and decoding in communication systems, and in particular, to sequence estimation techniques with reduced complexity.
2. Discussion of the Prior Art
A limiting factor in the performance of digital communication systems which are designed to transmit digital data over a time-dispersive channel is intersymbol interference (ISI).
FIG. 1
shows the block diagram for a conventional receiver
100
in a channel environment associated with, for example, the Gigabit Ethernet 1000 Base-T standard. As shown in
FIG. 1
, the receiver
100
includes an analog-to-digital (A/D) converter
110
for converting the received analog signal to a digital signal. The digitized data is then processed by a feed forward equalizer (FFE)
120
; an echo canceller
130
and a crosstalk canceller
140
. Generally, the feed forward equalizer (FFE)
120
makes the channel impulse causal, and additionally whitens the noise. In addition, the echo canceller
130
removes echo from the received signal and the crosstalk canceller
140
removes the crosstalk, as is well known in the art. The equalizer/decoder
150
performs data detection, for example, using maximum likelihood sequence estimation (MLSE), to produce output symbols or bits.
It is well known that MSLE is the optimum method for the recovery of a data sequence in the presence of ISI and additive white Gaussian noise (AWGN). For a more detailed discussion of a maximum likelihood sequence estimation (MLSE), see G. D. Forney Jr., “Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference,” IEEE Trans. Inform. Theory, vol. IT-18, pp. 363-378, May 1972, incorporated by reference herein.
The Viterbi Algorithm is a computationally efficient implementation of MLSE, however, it requires an excessive amount of computing power for most practical channels found in broadband communication systems. For a more detailed discussion of the Viterbi algorithm, see G. D. Forney, Jr. “The Viterbi Algorithm,” Proc. IEEE, vol. 61, pp. 268-278, March 1973. Several sub-optimal modifications to the Viterbi algorithm have been introduced to reduce the computational complexity of the Viterbi algorithm. One such technique is reduced state sequence estimation (RSSE). Referring to
FIG. 1
, block
150
, the equalizer/decoder may be implemented as an RSSE circuit. Two special cases of RSSE are Decision-feedback sequence estimation (DFSE), and parallel decision feedback decoding (PDFD). DFSE employs a trellis that takes into account only the first K of the L channel coefficients {f
i
}, 1≦i≦L, where L is the channel memory. PDFD is a special case of DFSE when K=0, where the reduced trellis becomes the TCM code trellis and decision feedback equalization is performed for each code state based on its survivor history. For a discussion of reduced state sequence estimation (RSSE) techniques and for the special cases (i.e., DFSE and PDFD), see, for example, P. R. Chevillat and E. Eleftheriou, “Decoding of Trellis-Encoded Signals in the Presence of Intersymbol Interference and Noise”, IEEE Trans. Commun., vol. 37, 669-76, (July 1989) and M. V. Eyuboglu and S. U. H. Qureshi, “Reduced-State Sequence Estimation For Coded Modulation On Intersymbol Interference Channels”, IEEE JSAC, vol. 7, 989-95 (August 1989), each incorporated by reference herein. RSSE is well suited for implementation in dedicated hardware due to its high parallelism, unlike other reduced complexity sequence estimation techniques such as the M-algorithm. For a discussion of M-algorithms (MA), see, for example, N. Seshadri and J. B. Anderson, “Decoding of Severely Filtered Modulation codes Using the (M,L) Algorithm”, IEEE JSAC, vol. 7, 1006-1016 (August 1989), incorporated by reference herein. Although RSSE has been proposed as a means to reduce the computational complexity of MLSE, the hardware cost of RSSE can still be very high.
FIG. 2
is an implementation of an RSSE equalizer/decoder which attempts to reduce the intersymbol interference associated with all channel coefficients, {f
i
}, 1≦i≦L, of the channel impulse response with memory L. The R decision feedback cells
209
of
FIG. 2
compute R ISI estimates in the decision feedback unit (DFU)
208
based on the survivor symbols from the corresponding survivor path cells
207
of
FIG. 2
in the survivor memory unit (SMU)
206
. These estimates are fed into the branch metric unit (BMU)
202
in which each branch metric cell
203
of
FIG. 2
computes the b metrics for the transitions emanating from the corresponding state. In the add/compare select unit (ACSU)
204
each add/compare select cell selects the best survivor path among all paths entering the state.
While RSSE reduces the complexity of MLSE, its hardware costs can still be very high in practical applications. To reduce the hardware costs of RSSE, it has been proposed to account only for the ISI introduced by the first U taps of the channel impulse response, {f
i
}, 1≦i≦U with an RSSE structure
302
, as shown in
FIG. 3
, and cancel the remaining ISI with a simple equalizer structure
304
. Referring again to block
150
of
FIG. 1
, it was previously stated that block
150
could be implemented as structure
200
of FIG.
2
. Structure
300
of
FIG. 3
represents another possible structure to implement block
150
to reduce the complexity of MLSE.
FIG. 4
is an illustration of the RSSE structure
302
of FIG.
3
. In the decision feedback unit (DFU)
408
each decision feedback cell
409
takes care of the ISI introduced by the first U channel coefficients, {f}, 1≦i≦U, where the number U is predetermined. The ISI from only the first U channel coefficients are considered in the RSSE apparatus
302
of
FIG. 3
based on an assumption that the channel impulse response which is seen by the equalizer/decoder (See block
150
of
FIG. 1
) is concentrated in the first U taps, as shown by the graph of signal energy v. coefficient index, i, in
FIG. 5
a
. Further, Block
304
of
FIG. 3
reduces the intersymbol interference from other than the first U taps, {f
i
}, U+1≦i≦L. This assumption is often valid for a minimum phase channel, however, in general the channel impulse response may be concentrated in taps other than the first U taps (e.g. Gigabit Ethernet over copper), or components in the tail of the channel impulse response may be significant. Furthermore, the distribution of the channel impulse response may change over time. As such, the channel energy will be concentrated in different taps as a function of time.
FIG. 5
b
illustrates a channel impulse response graph with significant channel coefficients in the tail. In these cases the reduced complexity RSSE equalizer/decoder
300
of
FIG. 3
, would exhibit significantly inferior performance. Thus, there is a need for a low computationally complex RSSE equalizer/decoder that exhibits acceptable performance in a wide variety of channel impulse responses and which is adaptively reconfigurable in response to changing channel environments and does not change the number of states as disclosed in the prior art.
SUMMARY OF THE INVENTION
The present invention provides an apparatus and method for reducing the computational complexity of the RSSE technique by reducing the intersymbol interference caused by significant channel coefficients with a tap selectable TS-RSSE (i.e., high complexity equalization and decoding algorithm). The more significant channel coefficients are adaptively selected in response to changes in the channel impulse response. Further, the intersymbol interference caused by the less significant channel coefficients is processed by a tap selectable decision feedback prefilter TS-DFP (i.e., a low complexity equalization algorithm). Referring again to
FIG. 1
, which is an illustration of the channel environment associated with, for example, the Gigabit Ethernet 1000 Base-T standard, the equalizer/decoder of the pre
Blanksby Andrew J.
Haratsch Erich Franz
Agere Systems Inc.
Chin Stephen
Hughes Ian M.
Mendelsohn Steve
Munoz Guillermo
LandOfFree
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