Method and apparatus for reduced latency in hold bus cycles

Details Method and apparatus for reduced latency in hold bus cycles Method and apparatus for reduced latency in hold bus cycles

1993-07-16

1995-03-14

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3408255, H04J 300

Patent

active

053982444

ABSTRACT:
An innovative protocol and system for implementing the same enables quick release of the bus by the master device, such as a CPU, to permit slave devices access to the bus. In one embodiment, the arbiter can select between the original hold protocol and quick hold protocol according to predetermined criteria which indicates that a low latency response is requested. Upon assertion of a QHOLD signal, the CPU issues a burst last signal to prematurely terminate outstanding burst transactions on the bus in a manner transparent to the slave devices. Once the outstanding bus cycles are complete, the CPU performs an internal backoff to immediately release the bus for access by the slave device requesting access. Any pending burst cycles which were terminated prematurely by the QHOLD signal, are subsequently restarted for the data not transacted by the CPU after the slave device completes access to the bus. The internal backoff mechanism is similarly transparent to the slave devices and does not cause a backoff signal to be issued to the peripherals or devices coupled to the bus. Thus, the addition of a quick hold protocol is added without significant modification of the slave devices' bus interface.

REFERENCES:
patent: 4623886 (1986-11-01), Livingston
patent: 4818985 (1989-04-01), Ikeda
patent: 5276684 (1994-01-01), Pearson
patent: 5287481 (1994-02-01), Lin

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