Method and apparatus for recovering from correctable ECC errors

Details Method and apparatus for recovering from correctable ECC errors Method and apparatus for recovering from correctable ECC errors

1997-06-23

1999-06-15

Grant, William

Excavating

371 102, 371 4014, 39518214, 39518215, G11C 2900

Patent

active

059129069

ABSTRACT:
On-chip delivery of data from an on-chip or off-chip cache is separated into two buses. A fast fill bus provides data to latency critical caches without ECC error detection and correction. A slow fill bus provides the data to latency insensitive caches with ECC error detection and correction. Because the latency critical caches receive the data without error detection, they receive the data at least one clock cycle before the latency insensitive caches, thereby enhancing performance if there is no ECC error. If an ECC error is detected, a software trap is executed which flushes the external cache and the latency sensitive caches that received the data before the trap was generated. If the error is correctable, ECC circuitry corrects the error and rewrites the corrected data back to the external cache. If the error is not correctable, the data is read from main memory to the external cache.

REFERENCES:
patent: 5341487 (1994-08-01), Derwin et al.
patent: 5517626 (1996-05-01), Archer et al.

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