Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1998-06-30
2001-10-23
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S262000, C708S290000
Reexamination Certificate
active
06307900
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a digital data detection method and an apparatus therefor; and, more particularly, to a method and apparatus for detecting recorded data based on an asynchronous data sampling technique.
DESCRIPTION OF THE PRIOR ART
In a conventional digital data recording/detection system, digital data serves to modulate the current in a recording/reproducing head assembly so that magnetic flux transitions of corresponding sequences are recorded onto a magnetic storage medium, such as a magnetic tape or a magnetic disk, at a predetermined recording rate, wherein the magnetic flux transitions of the corresponding sequences take the form of analog signals. When a recorded signal is reproduced, the recording/reproducing head assembly again passes over the magnetic storage medium and transduces the magnetic transitions into pulses of an analog signal that alternate in polarity. Thereafter, these pulses are amplified by a pre-amplifier and then sampled into digitized data by an A/D converter. Decoding the digitized data into a digital bit stream can be performed by a discrete time sequence detection.
Referring to
FIG. 1
, there is shown a schematic block diagram for a conventional digital data detection system for reproducing recorded digital data, disclosed in U.S. Pat. No. 5,696,639 entitled “Sampled Amplitude Read Channel Employing Interpolated Timing Recovery”. The conventional digital data detection system comprises a magnetic storage medium
10
, an analog signal acquisition circuit
20
, a pre-amplifier
30
, an A/D converter
40
, a discrete time equalizer filter
50
, an interpolation circuit
60
, a discrete time sequence detector
70
, a data sync detector
80
, a RLL (Run Length Limited) decoder
90
, a frequency generator
100
, and a gain control block
110
.
The magnetic storage medium
10
includes data recorded in the form of analog signals, wherein the data is representative of a video or an audio signal, or the like. The analog signal acquisition circuit
20
receives data signals from the magnetic storage medium
10
obtained through a reproducing head assembly (not shown) included therein. Thereafter, the reproduced analog data signals are amplified by the pre-amplifier
30
.
When the amplified analog data signals denoted by Y(t) are sampled by the A/D converter
40
in response to a sampling clock provided from the frequency generator
100
, wherein the sampling clock has a slightly higher frequency than a recording clock so that the amplified analog data signals are sampled faster than the recording clock rate. The sampling clock
200
is adjusted by a channel data rate (CDR) control signal corresponding to the data record rate. Also, the frequency generator
100
provides the discrete time equalizer filter
50
and the interpolation circuit
60
with the sampling clock
200
for synchronizing same.
After receiving the sampled digital data signals from the A/D converter
40
, the discrete time equalizer filter
50
provides further equalization of the sampled digital data signals inputted thereto toward the desired response. The equalized digital data signals are then transmitted to the interpolation circuit
60
.
Referring to
FIG. 2
, there is illustrated a detailed block diagram of the interpolation circuit
60
according to the prior art. As shown in
FIG. 2
, the interpolation circuit
60
includes an interpolator
61
, an AND gate
63
, a zero phase start block
64
, and a phase error detection block
250
. The phase error detection block
250
contains an MOD-TS accumulator
62
, a loop filter
65
, a phase error detector
66
, a multiplexer
67
, an expected sample generator
68
, and a slicer
69
.
The interpolator
61
may be described with reference to
FIG. 3
which shows an obtained analog signal
300
. Target data values are shown as black circles and sampled data values are depicted with arrows. Below the obtained analog signal
300
, there are illustrated a timing diagram depicting the corresponding timing signals for the sampling clock
200
, a data clock
210
and a mask signal
220
. As can be seen in
FIG. 3
, the obtained analog signal
300
in the analog signal acquisition circuit
20
is sampled slightly faster than the recording clock rate by the A/D converter
40
.
The function of the interpolator
61
is to estimate the target data values by interpolating the sampled data values, wherein the interpolator
61
has a FIR (Finite Impulse Response) filter structure. A simple estimation algorithm as follows is assumed:
Y
(
N
−1)=
x
(
N
−1)+&tgr;{
x
(
N
)−
x
(
N
−1)} (Eq. 1)
wherein x(N−1) and x(N) are the sampled data values surrounding the target data value Y(N−1); and &tgr; is an interpolation interval proportional to a time difference between the sampled data value x(N−1) and the target data value Y(N−1). Referring to again
FIG. 2
, the interpolation interval &tgr;
230
is outputted from the MOD-Ts accumulator
62
which accumulates a frequency offset signal &Dgr;f:
&tgr;=(&Sgr;&Dgr;
f
) MOD
Ts
(Eq. 2)
wherein Ts is the sampling period of the sampling clock
200
. Since the sampling clock
200
samples the amplified analog data signals Y(t) at a rate slightly faster than the recording clock rate, it is necessary to mask the data clock
210
whenever the accumulated frequency offset &Dgr;f
240
, integer divided by Ts, is increased by 1. Operation of the data clock
210
from the AND gate
63
and the mask signal
220
generated by the MOD-Ts accumulator
62
can be understood with reference to the timing diagram of FIG.
3
.
Assuming the interpolator
61
implements the simple linear Eq. 1 above, then sampled data values
302
and
304
are used to generate an interpolated data value corresponding to a target data value
306
. The interpolation interval &tgr;
308
is generated according to Eq. 2 above. A next interpolated data value corresponding to the next target data value
310
is computed from sampled data values
304
and
312
. This process continues until the interpolation interval &tgr;
314
becomes greater than Ts except that it wraps around and becomes actually &tgr;
316
. At this point, the data clock
210
is masked by the mask signal
220
, so that an interpolated data value corresponding to a target data value
320
is computed from sampled data values
322
and
324
rather than sampled data values
318
and
322
.
Referring back to
FIG. 2
, the expected sample generator
68
, responsive to the interpolated data values
260
, generates expected data values to be used by the phase error detector
66
to compute a phase error during acquisition. The multiplexer
67
selects estimated data values from the slicer
69
for use by the phase error detector
66
during tracking.
The phase error detector
66
and the slicer
69
process the interpolated data
260
at the output of the interpolator
61
rather than the equalized digital data value
270
at the output of the discrete time equalizer filter
50
. The loop filter
65
controls the closed loop frequency response. The zero phase start block
64
minimizes the initial phase error between the sampling clock
200
and the amplified analog signal Y(t).
Returning to
FIG. 1
, the data clock
210
, which is generated at the output of the AND gate
63
in response to the sampling clock
200
from the frequency generator
100
and the mask signal
220
from the MOD-Ts accumulator
62
, is transmitted from the interpolation circuit
60
to the discrete time sequence detector
70
, the data sync detector
80
, the RLL (Run Length Limited) decoder
90
, and the gain control block
110
. Also, the interpolated data
260
is sent to the discrete time sequence detector
70
. The discrete time sequence detector
70
, such as a maximum likelihood (ML) Viterbi sequence detector, detects estimated sequences using the interpolated data and the data clock inputted thereto from the interpolation circuit
60
. Thereafter, the discrete time sequenc
Anderson Kill & Olick, P
Chin Stephen
Daewoo Electronics Co. Ltd.
Deppe Betsy L.
LandOfFree
Method and apparatus for recovering digital data by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for recovering digital data by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for recovering digital data by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2607854