Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Patent
1996-06-07
1998-05-26
Hoff, Marc S.
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
341101, H03M 900
Patent
active
057572976
ABSTRACT:
A serial data stream is recovered using a local clock, which is asynchronous to the clock used to transmit the serial data. The incoming serial data stream is phase shifted or delayed by a digital phase-locked loop so that it may be reliably sampled by the local clock. The DPLL samples the serial data stream and captures data on both the rising and falling edges of the local clock employing three edge detectors. This partitions the data stream into two bit samples, which the DPLL presents to a deserializer. The deserializer converts the serial data to parallel data and assembles the received data back into data bytes. The deserializer also generates a received byte clock used for presenting the parallel data to, for example, the ESCON channel logic.
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Ferraiolo Frank David
Hoke Joseph Michael
Patel Samir Kirit
Cutter Lawrence D.
Hoff Marc S.
International Business Machines - Corporation
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