Method and apparatus for reconfigurable frequency generation

Details Method and apparatus for reconfigurable frequency generation Method and apparatus for reconfigurable frequency generation

2011-01-11

2011-01-11

Pham, Tuan A (Department: 2618)

Telecommunications

Transmitter and receiver at same station

With frequency stabilization

C455S075000, C455S102000, C455S108000, C455S110000, C375S215000, C375S242000, C375S268000, C375S294000

Reexamination Certificate

active

07869769

ABSTRACT:
A frequency generator (100) takes a signal source (clock or carrier) (101) and generates a edge encoded direct digital modulated differential output signal (110). The differential signal (110) is applied to a frequency extension quadrature generator (FEQG) (112). The FEQG (112) includes a fractional differential wavelength delay locked loop (DLL) (280) and a frequency multiplier (240). The DLL (280) generates a control voltage (214) with which to control delays of the edge encoded modulation signal (110). A frequency extended quadrature function is applied to the periodic steady state input signal with edge encoded modulation (110), to provide the output signal set113.

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Ramin Farjad-Rad et al; “A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly Integrated Digital Chips”; IEEE Journal of Solid-State Circuits., vol. 37, No. 12; pp. 1804-1812; Dec. 2002.

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