Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – By integrating
Reexamination Certificate
2000-01-06
2002-05-28
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific input to output function
By integrating
C327S319000, C327S333000
Reexamination Certificate
active
06396329
ABSTRACT:
The present invention relates generally to a high frequency digital signal receiver, and more particularly to a digital signal receiver that uses integration techniques to reduce latency of signals on a bus.
BACKGROUND OF THE INVENTION
An efficient high speed signaling system requires the use of well-controlled waveforms. For example, in a high speed signaling system with a clock cycle time in the range of approximately one to two nanoseconds, the amplitude of the voltage swing, the rise and fall times, and the duty cycle of the signaling waveform should be within well-defined limits. The term “voltage swing” refers to a difference between a minimum predetermined voltage and a maximum predetermined voltage of a signal. For example, typical limits may include a voltage swing of approximately one volt, a near fifty percent duty cycle, and a rise and a fall time of approximately one hundred picoseconds (ps). In some systems, the voltage swing of CMOS signals ranges from a low of zero volts to a high of five volts. In other systems, the voltage swing of the CMOS signals ranges from a low of zero volts to a high of 2.5 volts.
A receiver system that receives and converts the high-speed, low swing waveforms to CMOS signals requires careful design, especially when multiple high-speed waveforms are received simultaneously and where noise is a significant factor.
The following naming convention will be used for signals. For example, the name “system clock” will refer to one signal, while that signal's complement will be referred to as “system clock B” or “system clock_b.” In other words, the complement of a signal will have an upper or lower case “b” following its name.
As shown in
FIG. 1
, a prior art sampling receiver
100
has a sense-amplifier
102
and a latch
104
. The sense amplifier
102
receives, senses and amplifies small changes in the input signal, Data In, with respect to a reference voltage Vref, and outputs a differential signal, A and A_b. The latch
104
amplifies, stores and converts the differential signal, A and A_b, to predetermined low and high values.
Referring also to the timing diagram of
FIG. 2
, a system clock and its complement, system clock_b, control the operation of the sampling receiver
100
. When system clock_b is transitions low the sense amplifier
102
is disabled. Two linear load/precharge transistors
112
,
114
become active and pull signals A and A_b at nodes N
A
and N
A
—
b
to a high voltage level.
When system clock_b transitions high, the sense amplifier
102
is enabled and senses the voltage of the data input signal, Data In. The two linear load transistors
112
,
114
become inactive. When the voltage of the data input signal, Data In, at the gate of input transistor
116
exceeds the reference voltage V
REF
at the gate of transistor
118
, the input transistor
116
becomes active and pulls output signal A_b to a low voltage level via a current sink
120
. When the data input signal is less than or equal to the reference voltage V
REF
, the input transistor
116
is inactive (i.e., or at least less conductive than transistor
118
) and the output signal A_b remains high.
The cross-coupled transistor pair
122
,
124
stores the state of signals A and A_b. Initially, when system clock_b is low, transistors
112
and
114
are enabled and act as linear load devices to the differential pair
116
,
118
. When system clock_b transitions high, transistors
112
and
114
become inactive and the cross-coupled pair
122
,
124
is enabled to sense and amplify variations of the input data signal, Data In. When the voltage of the input signal, Data In, is less than the reference voltage V
REF
, transistor
118
is active and pulls the voltage of signal A at node N
A
to ground, which causes the voltage of signal A_b at node N
A
—
b
to transition high. When the voltage of the input signal Data In exceeds the reference voltage V
REF
, transistor
116
becomes active and pulls the signal A_b at node N
A
—
b
low; in addition, transistor
118
becomes inactive and the signal A_b at node N
A
—
b
is pulled high. The cross-coupled pair
122
,
124
acts as an amplifier for small changes in the voltage of the input signal Data In with respect to the reference voltage V
REF
.
When system clock_b transitions low, sense amplifier
102
is disabled and the complementary output signals A and A_b from the sense amplifier
102
are stored in latch
104
. Latch
104
is enabled by the system clock.
In latch
104
, an equalizing transistor
126
becomes active when the system clock transitions low and drives the output signals Out and Out_b to the same voltage level. When the system clock transitions high, the equalizing transistor
126
becomes inactive, latch-enable transistors
128
,
130
become active and enable the latch-data-input transistors
132
,
134
to act as a pull-down circuit when responding to the differential output signals A and A_b from the sense amplifier
102
. In particular, when the system clock is high, the latch-data-input transistors
132
,
134
are responsive to the amplified signals A and A_b. A four transistor latch circuit
136
latches the associated state of signals A and A_b, and generates the latched-output signals, Out
142
and Out_b
144
. The four transistor latch circuit
136
includes transistors
152
,
154
,
156
and
158
.
When the system clock transitions low, latch-enable transistors
128
,
130
become inactive thereby causing the latch
104
to become non-responsive to signals A and A_b. In this way, the latch
104
captures the state of A and A_b at the high-to-low transition of the system clock. To reduce the probability of errors caused by noise, the timing of the high-to-low transition of the system clock should occur at a time when the differential amplitude between the A and A_b signals is greatest. In addition, when a system has multiple receivers and drivers operating simultaneously, the likelihood of noise injection on V
REF
and, consequently, errors is increased.
The circuit of
FIG. 2
senses even data values, D
0
and D
2
, in response to the falling edge of the system clock, and latches the even data values in response to the rising edge of the system clock. Another circuit, similar to the circuit of
FIG. 2
, operates on opposite clock edges senses and latches odd data values (e.g., sensing in response to the rising edge of the system clock) and latching in response to the falling edge of the system clock.
A Prior Art Integrating Receiver
In
FIG. 3A
, an integrating receiver
180
improves performance in a noisy environment. The integrating receiver
180
is a type of matched filter. In the integrating receiver
180
, an integrator
182
, a sample-and-hold (S/H) circuit
184
, an amplifier
186
and a latch
188
are connected in series and receive and output differential signals. The integrating receiver
180
integrates a bias current I
BIAS1
based on the difference between the differential input signals V
IN
+ and V
IN
− over a given period of time, called the integration interval. Prior to the start of the integration interval, the output value of the integrator
182
is initially set equal to zero volts. After integration is complete and additional processing, the latch
188
stores the result of the integration.
Referring also to
FIG. 3B
, the integrating receiver
180
operates according to three phases—an integration phase (Phase I), a hold phase (Phase II) and a latch phase (Phase III). A first timing signal &phgr;
192
and a second timing signal &PSgr;_b
194
define the phases and control the operation of the integrating receiver
180
. The first timing signal &phgr; defines the integration interval or phase and is a clock that operates at the system clock frequency. The second timing signal &PSgr;_b defines the hold and latch phases when the first timing signal &phgr; is no longer in the integration phase. In some implementations, the first timing signal &phgr; is phase shifted with respect to the system clock.
During Phase I, the integration interval, when t
Callahan Timothy P.
Nguyen Hai L.
Pennie & Edmonds LLp
Rambus Inc
LandOfFree
Method and apparatus for receiving high speed signals with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for receiving high speed signals with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for receiving high speed signals with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2856394