Pulse or digital communications – Synchronizers
Reexamination Certificate
1999-12-30
2003-08-12
Bayard, Emmanuel (Department: 2731)
Pulse or digital communications
Synchronizers
Reexamination Certificate
active
06606360
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to methods and apparatuses for receiving data, and more particularly to a method and apparatus for receiving data in a noisy environment, such as a server.
BACKGROUND OF THE INVENTION
Two basic data-receiver architectures are prevalent in the communications and computer industries today—tracking receivers and over-sampling receivers. In short, a tracking receiver employs a phase locked-loop—(PLL) based architecture that compares the phase of the received data with a local clock phase and modulates the frequency of the local clock to match the rate of the incoming data. A tracking receiver therefore tracks the frequency of the received data so that the tracking receiver can reliably receive the data. By tracking the frequency of the received data, the receiver can tolerate phase and amplitude jitter that may be present in the received waveform due to multiple noise sources. An alternate implementation of a tracking receiver employs a delayed-locked loop (DLL), which serves a similar function as the PLL. For purposes of this application, the comments herein regarding PLLs are generally applicably to DLLs, as well.
An oversampling receiver avoids the use of a phase-locked-loop-based architecture by taking many samples of the received data and looking at the history of those samples to filter out noise in the data. The many samples taken by an over-sampling receiver are at a frequency which is some multiple (e.g., 3 times) of the nominal frequency (without phase and amplitude jitter) of the received data. By taking many samples of the received data, the transmitted signal can be determined, and there is no need to modulate the clock frequency of the receiver.
Tracking receivers require analog circuits that are sensitive to noise. Often the designs of tracking receivers are large and/or need additional power to function correctly in integrated circuits that contain a large amount of high frequency digital logic circuitry, such as a microprocessor, memory controller or I/O (input/output) bridge. Extreme care must be taken when laying out a circuit board for a receiver that includes very sensitive analog circuits (i.e., a phase-locked loop circuit) and very high speed digital logic, which draws down the voltage rails very quickly causing large noise sources. Consequently, circuit designers employ various techniques to lessen the impact of these noise sources on the sensitive analog circuits, however, these techniques often result in increased circuit costs (both in size and investment).
In general, over-sampling receivers contain a much higher percentage of digital circuitry than tracking receivers, and therefore should be more tolerant of noise sources. However, the rate at which over-sampling receivers sample the incoming waveform introduces an additional source of jitter, often called quantization jitter, which reduces the noise budget in the transceiver/channel subsystem. As the rate of the oversampling is at least three times the data rate, the speed of the digital logic limits the overall speed of the communication process to a much lower rate than otherwise possible using a tracking receiver. Consequently, very high speed receivers usually employ phase-locked loop circuits to enable operation of the receiver closer to the limit of the digital circuitry.
The invention is therefore directed to the problem of developing a digital receiver that can operate at the speed of the digital circuitry, yet does not require sensitive analog circuits.
SUMMARY OF THE INVENTION
One embodiment of the invention comprises a method and apparatus to asynchronously receive a stream of data. The method and apparatus operate to detect edges within the stream of data and track a transmitted clock using multiple locally-generated clock phases. Moreover, the method and apparatus determine whether each edge arrives early or late relative to an expected arrival time and use the determination whether an edge arrived early or late in a receiver decision process.
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Abhayagunawardhana Chamath
Dunning David S.
Bayard Emmanuel
Fortkort Michael P.
Intel Corporation
Mayer Fortkort & Williams PC
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