Method and apparatus for reassembly of data packets into message

Details Method and apparatus for reassembly of data packets into message Method and apparatus for reassembly of data packets into message

1996-07-23

1999-02-09

Pham, Chi H.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370399, 370474, H04L 1256

Patent

active

058703942

ABSTRACT:
An apparatus for receiving messages defined by data packets having respective header and payload portions where each header portion includes a channel representation regarding a channel associated with the data packet and an end of message representation representing whether or not the data packet is a final data packet in the message and where each payload portion includes information pertaining to the message. The apparatus includes data memory for storing the payload portions of the data packets, list memory, a header processor for receiving the header portion of the data packet and for providing status signals indicative of the channel representation and the end of message representation, and a reassembly processor programmed to maintain in the list memory a pointer list of address pointers to unused blocks of data memory and a link list of address pointers associated with each channel.

REFERENCES:
Author: International Telecom Union. Title: Integrated Services Digital Network (ISDN) Overall Network Aspects and Functions B-ISDN ATM Adaptive Layer (ALL) Type 5 Specification. pp. 1-27 and appendices. May 1996. Place of Pub.: Geneva, CH.
Author: Integrated Device Technology, Inc. Title: 155 Mb/s ATM Segmentation & Reassembly "SAR" Controller for the PCI Local Bus IDT77201 data sheet. pp. 1-11. Apr. 1994. Place of Pub.: United States.
Author: Transwitch Corp. Title: ATM Technology & Applications Seminar. Jan. 1995. Place of Pub.: United States.

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