Method and apparatus for reading packet-oriented data signals in

Multiplex communications – Wide area network – Packet switching

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Details

370 941, 3701053, 364939, 36494061, 36494831, 364239, 364284, 36424294, 36423951, 375117, H04L 700

Patent

active

049224387

ABSTRACT:
A method and apparatus for controlling read-in and read-out of serial or parallel packet-oriented data signals with respect to a buffer in a communication terminal provides for the identification of a packet start bit combination in incoming packet-oriented data signals before initialization of the reading of the data signals into the buffer and initialization for reading out the data signals after a prescribed delay time with reading terminated after the identification of a packet end bit combination and/or a bit combination indicating stuffing bits between end and start bit combinations. Read-out is terminated after the identification of a packet end bit combination or of a bit combination indicating stuffing information at the data output of the buffer or given equality of the read-in and read-out addresses, assuming a packet end bit combination and/or a bit combination indicating stuffing information is identified at the data output of the buffer. The method and apparatus serve the purpose of phase and clock frequency matching between the data bit clock of the incoming data signals and the processing clock of a communication terminal in, for example, a ring-shaped network.

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