Method and apparatus for rapidly switching processes in a comput

Details Method and apparatus for rapidly switching processes in a comput Method and apparatus for rapidly switching processes in a comput

1992-05-08

1994-11-01

Shaw, Dale M.

395425, G06F 938

Patent

active

053613376

ABSTRACT:
An apparatus and method are disclosed for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs. To date, processors either stay idle or execute instructions out of order when they encounter cache misses. As the speed of processors become faster, the penalty for a cache miss is heavier. Having multiple copies of state elements on the processor and coupling them to a multiplexer permits the processor to save the context of the current instructions and resume executing new instructions within one clock cycle. The invention disclosed is particularly useful for minimizing the average instruction cycle time for a processor with a main memory access time exceeding 15 processor clock cycles. It is understood that the number of processes who's states are duplicated may easily be a large number n.

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