Electricity: motive power systems – Positional servo systems – Pulse-width modulated power input to motor
Reexamination Certificate
2001-01-06
2002-07-23
Nappi, Robert E. (Department: 2837)
Electricity: motive power systems
Positional servo systems
Pulse-width modulated power input to motor
C388S804000, C388S811000, C388S819000, C388S831000
Reexamination Certificate
active
06424113
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a method and apparatus for pulse width modulation, and more particularly, to a method and apparatus for pulse width modulation for an inverter circuit of a motor.
BACKGROUND
Most adjustable speed and torque drives are powered by an inverter. An inverter converts DC voltage or current to an AC waveform. The inverter consists of a DC source supplying voltage or current to a number of controllable switches. Pulse width modulation (PWM) is a method of controlling the inverter switching pattern to produce the desired amplitude and frequency of the output voltage or current. There are numerous forms of PWM. Sine-triangle PWM is one of the simplest to implement. In sine-triangle PWM a desired voltage waveform is compare to a triangle waveform, called the carrier signal. The pulse width is determined by the intersection of the two signals as shown in FIG.
1
.
For a three-phase system, the maximum line-to-line voltage produced by Sine-Triangle PWM is 0.866 VDC or 86% of the DC supply. It has been shown that adding triplen harmonics to the phase voltage commands increases the line-to-line output voltage possible, without adding harmonic distortion to the machine.
The Space Vector PWM (SVPWM) is a PWM method that is equivalent to adding the triplen harmonics to the phase voltages. However, instead of phase voltages, the SVPWM method is based on a complex voltage vector or voltage space vector. A voltage space vector represents a voltage distributed sinusoidally in space. An inverter feeding a machine with three equally, sinusoidally distributed windings can produce six non-zero space vectors and two zero space vectors. Each vector has an associated switching state, with “−” representing an open inverter switch and “+” meaning the switch is closed. As shown in
FIG. 2
, the non-zero vectors form six sectors within a hexagon.
The first task in realizing a given voltage space vector, is to determine which sector the vector resides. In
FIG. 3
, the given space vector Ua is spatially located between the vectors of switching states {+−−} and {++−}. The space vector Ua can be represented by projections, Ua
1
and USA, onto the two switching state vectors. However, to physically realize Ua, the inverter must divide the time spent in each switching state for a given time period. By toggling between states {−−−}, {+−−}, {++−}, and {+++} for specific time duration, an average value of Ua is produced.
In order to determine the appropriate time duration of each switching state, the projections of Ua onto those states must first be determined. The following equations determine the appropriate 5 switching duration for each switching state in a given time period of T
s
.
t
a1
=
T
s
2
U
a
3
π
(
cos
(
a
)
-
1
3
sin
(
a
)
)
t
a2
=
T
s
2
U
a
2
3
π
sin
(
a
)
t
a0
=
T
s
2
-
t
a1
-
t
a2
Computationally, SVPWM method is more complex than the sine-triangle PWM method. However, the benefit of SVPWM is a greater potential output voltage. As shown in
FIG. 4
, the two circular trajectories inscribed in the hexagon represent the maximum peak voltage space vectors for the two PWM methods mentioned while in the linear modulation region. For sine-triangle PWM, the maximum fundamental peak phase voltage is equal to half of the DC bus voltage. The addition of the triplen harmonics in SVPWM, results in a greater maximum fundamental peak phase voltage of V
dc
{square root over (v3+L )}. Due to the improved utilization of the DC voltage supply, the SVPWM method is the preferred PWM method, despite its computational complexity.
Recently, a method has been developed that eliminates the need for the trigonometric calculations in the SVPWM algorithm. In addition, this method simplifies the implementation of other forms of PWM such as 60° and 120° discontinuous, and allows for simplified overmodulation strategies. The method is based on the sine-triangle PWM, either discrete or analog, and realizes the other forms of PWM by adding an identical offset voltage (zero sequence voltage) to each of the phase voltage commands. An equivalent of SVPWM can be realized by using an offset voltage equal to the average of the maximum and minimum phase voltages as shown in FIG.
5
. The addition of the offset centers the phase voltages between +/−V
dc
/2. As a result, the phase voltages can be increased beyond the maximum magnitude possible when using the sine-triangle PWM alone. This method implicitly adds the triplen harmonics to the phase voltages by adjusting those voltages relative to the DC bus voltage limits.
The calculation of the offset voltage and its addition to the phase voltage commands can be easily implemented in a microprocessor, using only addition, multiplication, and compare instructions. For a three-phase system, a total of three add instructions are needed to shift the phase voltages.
FIGS. 5
a
-
6
d
shows examples of the offset voltage for SVPWM and three types of discontinuous PWM.
For a digital hardware implementation, the addition of the offset voltage to the phase voltage can be performed in either one of two ways. The digital hardware could have an arithmetic logic unit (ALU), which would sequentially add the offset to each of the reference voltages. However, the addition of an ALU to any hardware design adds complexity. Instead of an ALU, the addition of the offset to each of the phase voltages could be processed simultaneously. For every n phases, there would be n adder units
10
coupled to n comparator circuits
13
, which adjust each phase voltage in parallel as shown in FIG.
7
. An up/down counter
12
is coupled to a signal equal to the period divided by two. By counting the signal and coupling it to comparators
12
, comparators
12
generate the desired pulses for each phase. The advantage of this parallel processing design is decreased computational time and a less complex, combinatorial design. The disadvantage of this implementation is the hardware cost of the n Full Adder units.
For a digital hardware implementation, the addition of the offset voltage to the phase voltage can be performed in either one of two ways. The digital hardware could have an arithmetic logic unit (ALU), which would sequentially add the offset to each of the reference voltages. However, the addition of an ALU to any hardware design adds complexity. Instead of an ALU, the addition of the offset to each of the phase voltages could be processed simultaneously. For every n phases, there would be n adder units
10
coupled to n comparator circuits
13
, which adjust each phase voltage in parallel as shown in FIG.
7
. An up/down counter
12
is coupled to a signal equal to the period divided by two. By counting the signal and coupling it to comparators
12
, comparators
12
generate the desired pulses for each phase. The advantage of this parallel processing design is decreased computational time and a less complex, combinatorial design. The disadvantage of this implementation is the hardware cost of the n Full Adder units.
It is desirable to reduce costs particularly in high volume automotive applications by reducing the amount of components when implemented in the hardware used for providing pulse width modulation for a motor. When implemented in software it is desirable to reduce the number of computational steps to improve the efficiency of the microprocessor.
It is therefore an object of the invention to improve the system efficiency of a pulse with modulating circuit.
SUMMARY OF THE INVENTION
In one aspect of the invention, a circuit for pulse width modulating a motor having n phase windings where n is greater than one includes an adder for adding a voltage offset signal and a carrier timing signal to form an offset carrier timing signal. A plurality of comparators equal to the number of pha
Degner Michael W.
Kelly John William
Momcllovich Paul Theodore
Duda Rina I.
Ford Global Technologies Inc.
Nappi Robert E.
Stec Jennifer
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