Method and apparatus for pseudo-direct access to embedded memori

Details Method and apparatus for pseudo-direct access to embedded memori Method and apparatus for pseudo-direct access to embedded memori

1996-04-12

1998-10-27

Nguyen, Hoa T.

39518322, 39520009, G06F 1100, G06F 1516

Patent

active

058288252

ABSTRACT:
A method and apparatus are provided for testing memory locations of embedded memories or on-board caches of a micro-controller, a micro-processor or a CPU-based integrated circuit through use of a test access port (TAP) such as the IEEE TAP described in "IEEE Standard Test Access Port and Boundary-Scan Architecture" (IEEE Std. 1149.1-1990). The TAP is utilized to serially shift address, data and command information provided by an external host into respective fields of a memory access register (MEMACC) located within a memory interface unit (MIU) of the CPU-based IC. Responsive to the command information, the TAP requests access to the IC's memory bus via the MIU. Next, the address, data and command information for accessing the embedded memory are serially shifted into the MEMACC. If a read operation is specified by the command information, the MIU returns the data stored in the specified memory location of the embedded memory and replaces the data within the data field of the MEMACC with the newly retrieved data. If a write operation is specified by the command information, the MIU transmits the data held in the data field of the MEMACC to the memory location specified. Finally, the data, address and command information stored in the MEMACC are serially shifted out via the TAP to the external host which analyzes the data output therefrom.

REFERENCES:
patent: 4755937 (1988-07-01), Glies
patent: 5253347 (1993-10-01), Bagnoli et al.
"IEEE Standard Test Access Port And Boundary-Scan Architecture", IEEE Std 1149.1-1990, May 21, 1990.

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