Method and apparatus for providing two system architectures in a

Details Method and apparatus for providing two system architectures in a Method and apparatus for providing two system architectures in a

1995-06-07

1998-06-30

Harrell, Robert B..

G06F 930

Patent

active

057746869

ABSTRACT:
A processor having two system configurations is provided. The apparatus generally includes an instruction set unit, a system unit, an internal bus, and a bus unit. The instruction set unit, the system unit, and the bus unit are coupled together by the internal bus. The system unit is capable of selectively operating in one of two system configurations. The first system configuration provides a first system architecture, while the second system configuration provides a second system architecture. The bus unit is used for sending and receiving signals from the instruction set unit and the system unit. According to another aspect of the invention, the instruction set unit is capable of selectively operating in one of two instruction set configurations. The first instruction set configuration provides for the execution of instruction belonging to a first instruction set, while the second instruction set configuration provides for the execution of instructions belonging to a second instruction set.

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