Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2007-07-10
2007-07-10
Zarneke, David A. (Department: 2891)
Semiconductor device manufacturing: process
With measuring or testing
C257SE21525
Reexamination Certificate
active
11033008
ABSTRACT:
A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.
REFERENCES:
patent: 5149674 (1992-09-01), Freeman, Jr. et al.
patent: 5514892 (1996-05-01), Countryman et al.
patent: 5751065 (1998-05-01), Chittipeddi et al.
patent: 5923088 (1999-07-01), Shiue et al.
patent: 6144100 (2000-11-01), Shen et al.
patent: 6187658 (2001-02-01), Chittipeddi et al.
patent: 6232662 (2001-05-01), Saran
patent: 6365958 (2002-04-01), Ibnabdeljalil et al.
patent: 6384486 (2002-05-01), Zuniga et al.
patent: 6614091 (2003-09-01), Downey et al.
patent: 6675053 (2004-01-01), Baluswamy et al.
patent: 6765282 (2004-07-01), Schulz
patent: 6791196 (2004-09-01), Kwon et al.
patent: 6804808 (2004-10-01), Li et al.
patent: 7081679 (2006-07-01), Huang et al.
patent: 2002/0025417 (2002-02-01), Chisholm et al.
patent: 2003/0020163 (2003-01-01), Hung et al.
patent: 2005/0082577 (2005-04-01), Usui
patent: 2006/0281200 (2006-12-01), Cadouri
Wintgens, Carl; “Detailed Structural Analysis I of the Oki Electric Co. Ltd. L67Q4003 32-Bit Microcontroller with Optional Analyses”; Sep. 2004.
Downey Susan H.
Hess Kevin J.
Miller James W.
Yong Cheng Choi
Freescale Semiconductor Inc.
Hill Susan C.
King Robert L.
Zarneke David A.
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