Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1999-03-09
2001-09-25
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C326S030000, C326S086000
Reexamination Certificate
active
06294942
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to high speed signal networks and more specifically to a method and apparatus for providing self-terminating signal lines within a high speed signal network.
BACKGROUND OF THE INVENTION
To obtain maximum performance from a high speed signal network (e.g., a signal network between a microprocessor and various high speed components such as dynamic random access memory (DRAM), single data rate random access memory (SDRAM), double data rate random access memory (DDRAM), etc.), each signal line within the signal network is terminated with an impedance element (e.g., a resistor) that matches the characteristic impedance of the signal line when components are coupled thereto (i.e., the loaded line characteristic impedance of the signal line). Terminating a signal line with an impedance element that matches the signal line's loaded line characteristic impedance (i.e., impedance matching) prevents signal reflection as a signal travels down the signal line, and maximizes energy transmission efficiency. Further, impedance matching averts erroneous switching of other components coupled to the signal line due to signal reflections. If a signal line is loaded with bi-directional driver receivers, typically both ends of the signal line are terminated.
FIGS. 1A-3B
show prior art methods of terminating a signal line. In
FIG. 1A
, a signal line
101
is resistively terminated by a resistor
103
coupled between the signal line
101
and ground. The resistor
103
matches the loaded line characteristic impedance of the signal line
101
(e.g., the characteristic impedance of the signal line
101
with the modules “M” coupled thereto). In
FIG. 1B
the signal line
101
is terminated by coupling the resistor
103
between the signal line
101
and a positive voltage rail (V
DD
).
Both the termination configurations of
FIGS. 1A and 1B
function well at preventing signal reflection. However, both configurations dissipate substantial D.C. power. For example, the termination of
FIG. 1A
dissipates power when the signal level on the signal line
101
is high (e.g., V
DD
) and the termination of
FIG. 1B
dissipates power when the signal level on the signal line
101
is low (e.g., 0 volts).
FIG. 2
shows a conventional series terminator
201
for terminating the signal line
101
. The series terminator
201
comprises a series resistor
203
placed along the signal line
101
and a capacitor
205
connected (e.g., in parallel) between the signal line
101
and ground. The values for the series resistor
203
and the capacitor
205
are selected to provide the required termination for the signal line
101
. The proper selection of the series resistor
203
and the capacitor
205
depend on the characteristics of the loaded signal line
101
(e.g., the package inductance
207
of the components coupled thereto), and changing the loading of the signal line
101
(e.g., by changing, adding or removing components) can cause the signal line
101
to respond worse to an incident signal than if the signal line
101
were not terminated.
FIG. 3A
is a schematic diagram of an active terminator
301
that provides the advantages of both the termination configuration of
FIG. 1A
(e.g., resistive termination to ground) and the termination configuration of
FIG. 1B
(e.g., resistive termination to V
DD
) without significant D.C. power consumption. The active terminator
301
comprises a plurality of complimentary metal-oxide-semiconductor (CMOS) inverters, specifically a first CMOS inverter
303
coupled to a second CMOS inverter
305
. The input of the first CMOS inverter
303
is coupled to the output of the second CMOS inverter
305
at a terminal A, and the output of the first inverter
303
is coupled to the input of the second inverter
305
.
FIG. 3B
is a schematic diagram of the interconnected transistors forming the first and the second CMOS inverters
303
,
305
of FIG.
3
A. The first CMOS inverter
303
comprises a first p-channel transistor
307
(first PFET
307
) having a source coupled to V
DD
, a drain coupled to a node B and a gate coupled to the terminal A, and a first n-channel transistor
309
(first NFET
309
) having a source coupled to ground, a drain coupled to the node B and a gate coupled to the terminal A. The second CMOS inverter
305
comprises a second p-channel transistor
311
(second PFET
311
) having a source coupled to V
DD
, a drain coupled to the terminal A and a gate coupled to the node B, and a second n-channel transistor
313
(second NFET
313
) having a source coupled to ground, a drain coupled to the terminal A and a gate coupled to the node B.
In operation, assume initially that no signal is present on the terminal A so that the terminal A is at 0 volts. With the terminal A at 0 volts, the first PFET
307
is ON, and the first NFET
309
is OFF and the node B is pulled to V
DD
. With the node B at V
DD
, the second PFET
311
is OFF and the second NFET
313
is ON. With the second NFET
313
ON, the signal line
101
is effectively terminated to ground via the resistor formed by the channel of the second NFET
313
(similar to the resistive terminator of FIG.
1
A). Accordingly, the dimensions of the second NFET
313
are selected so that the channel resistance of the second NFET
313
matches the loaded line characteristic impedance of the signal line
101
. No D.C. current flows as terminal A is at 0 volts.
Thereafter assume a high voltage signal V
S
(e.g., V
S
=V
DD
) is incident on the active terminator
301
. Because the signal line
101
is terminated to ground, no portion of V
S
is reflected. However, D.C. current can flow from the terminal A to ground (via the second NFET
313
) and absent the operation of the active terminator
301
(described below) D.C. power would be wasted.
In response to the high voltage V
S
, the first PFET
307
turns OFF, the first NFET
309
turns ON and the node B is pulled to ground. In response thereto, the second PFET
311
turns ON, the second NFET
313
turns OFF. With the second PFET
311
ON, and the signal line
101
is effectively terminated to V
DD
via the resistor formed by the channel of the second PFET
311
(e.g., similar to the resistive terminator of FIG.
1
B). Accordingly, the dimensions of the second PFET
311
are selected so that the channel resistance of the second PFET
311
matches the loaded line characteristic impedance of the signal line
101
.
With the second PFET
311
ON, the signal line
101
remains effectively terminated to V
DD
, and D.C. current can no longer flow between the terminal A and ground. Because of the rapid turn ON time of the second PFET
311
in response to a high voltage signal on the terminal A, negligible D.C. power is lost.
The active terminator
301
behaves similarly when the signal V
S
switches from a high voltage level to a low voltage level (e.g., ground). The first PFET
307
turns ON, the first NFET
309
turns OFF, the second PFET
311
turns OFF and the second NFET
313
turns ON. The signal line
101
, therefore, is effectively terminated to ground, and negligible D.C. power is lost.
In terms of lower D.C. power consumption, the active terminator
301
is far superior to the passive resistive terminators of
FIGS. 1A and 1B
, and the active terminator
301
terminates more effectively than the passive series terminator of FIG.
2
. However, all of the forms of terminations described in
FIGS. 1A-3B
, as well as other prior art techniques for improving signal line transmission
10
(e.g., output current shape control, feedback circuits to adjust rise/fall times, limited swing terminations, etc.), require additional signal network components that consume valuable card space and that increase manufacturing costs (e.g., purchasing cost, storage cost, cost of placing the components on cards, etc.)
Accordingly, a need exists for a method and apparatus that provides effective signal line termination within a signal network without consuming significant D.C. power and without requiring extra terminating co
Bertin Claude L.
Bonaccio Anthony R.
Kalter Howard
Tonti William R.
Chadurjian Mark F.
Cunningham Terry D.
International Business Machines - Corporation
Schmeiser Olsen & Watts
Tra Quan
LandOfFree
Method and apparatus for providing self-terminating signal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for providing self-terminating signal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for providing self-terminating signal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2489973