Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-02-25
2004-08-03
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185290
Reexamination Certificate
active
06771541
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory, and more particularly to providing row redundancy in nonvolatile semiconductor memory.
2. Description of the Related Art
Nonvolatile semiconductor memory array retains stored data when power is removed. Many different types of nonvolatile data cells suitable for nonvolatile memory are known, including a class of single transistor devices that are based on the storage of charge in discrete trapping centers of a dielectric layer of the structure, and another class of devices that are based on the storage of charge on a conducting or semiconducting layer that is completely surrounded by a dielectric, typically an oxide. Techniques are also known for achieving multiple bit storage in a single transistor nonvolatile data cell by programming the multiple bits into a data cell as different voltage levels or in different parts of the cell. The trapped charge establishes the threshold voltage, or V
T
, of the device, which is sensed when the memory is read to determine the data stored therein.
An illustrative well known type of compact floating gate data cell structure is the stacked gate structure. A floating gate, typically a doped polysilicon layer, is sandwiched between two insulator layers, typically oxide. The top layer of the stack is a control gate electrode, typically a doped polysilicon layer. In one type of floating gate transistor, the stacked gate structure overlies part of a heavily doped n+ source region and a heavily doped n+ drain region, as well as a channel region between the source region and the drain region. The channel region is part of a p-well, which also contains the source region, the drain region, and a heavily p+ doped contact region. The p-well typically is contained within an n-type substrate or within an n-well, which also contains a heavily n+ doped contact region. The n-well is in turn contained in the p-type substrate. Many variations in the floating gate data cell structure are known, and include asymmetrical stacked gate structures, split gate structures, and so forth. Moreover, although the structure described herein is an n-channel enhancement mode device, nonvolatile data cells may be fabricated as either n-channel or p-channel devices or as enhancement or depletion mode devices.
As is typical of nonvolatile data cells that are capable of being repeatedly programmed and erased, the various functions of the stacked gate data cell are controlled by applying various bias voltages. The voltage applied to the control gate is V
G
, the voltage applied to the source is V
S
, the voltage applied to the drain is V
D
, the voltage applied to the p-well is V
P
, the voltage applied to the n-well is V
N
, and the voltage applied to the p-type substrate is V
B
. Typically the substrate is grounded, i.e. V
B
=0V. Typically writing or programming the data cell means adding negative charge to the floating gate while erasing the data cell means removing negative charge from the floating gate, but the charged state can be considered the erased state if desired. Other voltages are applied to read the charge state of the data cell by detecting the threshold voltage V
T
of the data cell, which ideally is done without disturbing the charge state.
Depending to some extent on device characteristics, stacked gate transistors may be programmed by moving electrons to the floating gate using Fowler-Nordheim (“FN”) tunneling or electron injection. Electron injection typically is done using channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). FN tunneling remains a popular choice in flash memory for erase operations.
A typical semiconductor memory contains millions of data cells. To avoid requiring that every one of the millions of data cells and associated connective structures in a non-volatile semiconductor memory device be error free and perfect, memory devices such as NOR-type flash memories often use redundant rows to repair bad rows. In one type of flash memory that supports sector erase, for example, a sector contains 512,000 bits of regular data cells (256 rows by 2K columns) and 32,000 bits of redundant cells (16 redundant rows by 2K columns.
During operation, conventional flash memories may be erased sector-by-sector using an embedded Sector Erase. However, if the data cells in the sector start out at different threshold voltages and only a sector erase operation is performed, some of the data cells may be erased near to or into depletion which will cause data errors in NOR-type flash memory products. To avoid this problem, a common practice for the embedded Sector Erase is to use a number of other operations in addition to the Sector Erase operation to prevent any of the data cells from being depleted.
The additional operations in common use for an embedded sector erase are Preprogram, Pre-Program Verify, Erase Verify (following the Erase operation), Post-Program Verify, and Post-Program. The first set of operations typically is a Pre-program followed by a Preprogram Verify. The objective of the Preprogram and Preprogram Verify operations is to program all of the cells in the selected sector, including the redundant cells, to a high V
T
, illustratively V
T
=5 volts, so that all of the cells can be erased from the same state. Both the Preprogram and Preprogram Verify operations are normally byte wide. The second set of operations typically is Erase followed by Erase Verify. All of the data cells including the redundant data cells in the selected sector are erased to a low V
T
, illustratively V
T
<3 volts. Erase is normally a bulk operation, and Erase Verify is normally a byte wide operation. The third set of operations typically is a Post-Program Verify followed by a Post-Program. All the cells including the redundant cells in the selected sector that fail Post-Program Verify, which occurs when they are erased too much (illustratively V
T
<0.5 volts), are Post-Programed and Post-Program Verified again so that all of the data cells in the selected sector have their threshold voltage V
T
in a range of from 0.5 volts to 3 volts, for example. The Post-Program Verify and Post-Program operations are normally byte wide operations. The Table of
FIG. 1
shows illustrative bias conditions for a selected sector of a flash memory array that uses CHE for programming and FN for erase, during each of the operations in an embedded sector erase. In unselected sectors, all of the row lines, columns, sources and the bulk remain grounded during all operations.
First, for the Preprogram operation, the source and bulk, used in this embodiment to refer to the p-well in which the data cell is fabricated (typically contained within a higher biased n-well, which in turn is in a grounded substrate), are biased at 0 volts for all cells in the selected sector, the selected row is biased at 10 volts, and the selected columns (typically one byte) is biased at 5 volts. Hot electrons are injected into the floating gate of the floating gate transistors in the selected data cells, which raises their threshold voltage V
T
. A suitably high V
T
value is V
T
=5 volts.
Next, for the Preprogram Verify operation, the source and bulk are biased at 0 volts for all cells in the selected sector, the selected row is biased at 6 volts, and the selected column is biased at 1 volt to sense the threshold voltage. If the threshold voltage is correct, no further programming of the particular data cell is performed. However, if the threshold voltage is not correct, the particular data cell is again Preprogrammed and Preprogram Verified until an acceptable threshold voltage is achieved.
Next, for the Erase operation, the source is floated, the bulk is biased at 6 volts for the selected sector, the rows of the selected sector are biased at minus 10 volts, and the columns of the selected sectors are floated. Electrons tunnel from the floating gates of the floating gate transistors in the selected data
Altera Law Group LLC
Hoang Huan
NexFlash Technologies, Inc.
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