Method and apparatus for providing redundancy in non-volatile me

Details Method and apparatus for providing redundancy in non-volatile me Method and apparatus for providing redundancy in non-volatile me

1999-05-06

2000-06-06

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, G11C 1600

Patent

active

060727233

ABSTRACT:
A bias circuit for a memory cell having first and second floating gate devices, and third and fourth reference devices, one of which has an output terminal coupled thereto is described. In one embodiment, the bias circuit includes a first capacitor including a first terminal coupled to the gates of the first and second devices, and a second terminal coupled to a power supply terminal, and a second capacitor including a first terminal coupled to the gates of the third and fourth devices, and a second terminal coupled to the power supply terminal. The bias circuit further includes a reference circuit including a first terminal having a first signal thereon and coupled to the gates of the first and second devices, and a second terminal having a second signal thereon and coupled to the gates of the third and fourth devices, the reference circuit to periodically turn on the first and second signals. The bias circuit reduces standby current and wake up time of redundant circuits in non-volatile memory devices.

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patent: 5296801 (1994-03-01), Ohtsuka et al.
patent: 5444659 (1995-08-01), Yokokura
patent: 5499217 (1996-03-01), Pascucci et al.
patent: 5859797 (1999-01-01), Maccarrone et al.

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