Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
1998-10-07
2001-04-10
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C710S008000
Reexamination Certificate
active
06216216
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer systems, and more particularly, but not by way of limitation, to a method and apparatus for providing processor partitioning on a multiprocessor machine.
BACKGROUND OF THE INVENTION
One of the key factors in the performance of a computer system is the speed at which the central processing unit (CPU) operates. Generally, the faster the CPU operates, the faster the computer system can complete a designated task. Another method of increasing the speed of a computer system is through the use of multiple CPUs. This is commonly known as multiprocessing. With multiple CPUs, algorithms required to complete a task can be executed substantially in parallel as opposed to their sequential execution, thereby decreasing the total time to complete the task.
However, as CPUs are dependent upon peripherals for providing data to the CPU and storing the processed data from the CPU, when a CPU needs to read or write to a peripheral, the CPU is diverted from a current algorithm to execute the read/write transaction. The length of time that the CPU is diverted is typically dependent upon the speed of the I/O transaction.
One advancement developed to increase the efficiency of I/O transactions is the intelligent input/output (I
2
O) architecture. In the I
2
O approach to I/O, low-level interrupts are off-loaded from a CPU to I/O processors (IOPs). The IOPs are additional processors that specifically handle I/O. With support for message-passing between multiple independent processors, the I
2
O architecture relieves the host processor of interrupt-intensive I/O tasks, greatly improving I/O performance especially in high-bandwidth applications such as networked video, groupware, and client/server processing.
Typical I
2
O architectures use a “split driver” model which inserts a messaging layer between the portion of the device driver specific to the operating system and the portion of the device driver specific to the peripheral. The messaging layer splits the single device driver of today into two separate modules, an Operating System Service Module (OSM), and a Downloadable Driver Module (DDM). The only interaction one module has with another module is through this messaging layer.
The OSM comprises the portion of the device driver which is specific to the operating system. The OSM interfaces with the operating system of the computer system (which is commonly referred to in the art as the “host operating system”) and is executed by the CPU. Typically, a single OSM may be used to service a specific class of peripherals. For example, one OSM would be used to service all block storage devices, such as hard disk drives, and CD-ROM drives.
The DDM provides the peripheral-specific portion of the device driver that understands how to interface to the particular peripheral hardware. To execute the DDM, an IOP is added to the computer system. A single IOP may be associated with multiple peripherals, each controlled by a particular DDM, and contains its own operating system such as, for example, the I
2
O Real-Time Operating System (iRTOS). The DDM directly controls the peripheral, and is executed by the IOP under the management of the iRTOS.
In general operation, the communications model used in the I
2
O architecture is a message passing system. When the CPU seeks to read or write to a peripheral in an I
2
O system, the host operating system makes what is known as a “request”. The OSM translates the request by the host operating system and, in turn, generates a message. The OSM sends the message across the messaging layer to the DDM associated with the peripheral which processes it appropriately to achieve a result. Upon completion of the processing, the DDM sends the result back to the OSM by sending a message through the messaging layer. To the host operating system, the OSM appears just like any other device driver.
By executing the DDM on the IOP, the time-consuming portion of transferring information from and to the peripheral hardware is off-loaded from the CPU to the IOP. With this off-loading, the CPU is no longer diverted for inordinate amounts of time during an I/O transaction. Moreover, because the IOP is a hardware component essentially dedicated to the processing of the I/O transactions, the problem of I/O bottlenecking is mitigated. Accordingly, any performance gains to be achieved by adding an additional or faster CPU to the computer system may be unhindered by the I/O processing bottleneck.
There are three common approaches to implement the I
2
O architecture. The first is an IOP installed on the motherboard of the computer system. In this approach, the IOP is installed directly on the motherboard and is used for I
2
O processing. In this particular configuration, the IOP is often used as a standard PCI bridge, and can also be used to bring intelligence to the PCI bus.
The second approach is to include an IOP on adapter cards, such that with an IOP on an adapter card, IT managers can add intelligent I/O to the computer system by adding an additional adapter.
The third approach is to install the IOP in the computer system via an optional plug-in card. This allows systems to be populated with one IOP per host adapter plugged into a slot instead of on the motherboard.
Although the intent of I
2
O was the implementation of portable, high-performance intelligent I/O systems, several problems remain with the I
2
O architecture. As is often the case, one problem is cost. The inclusion or the addition of additional hardware and extra processors (the IOPs) to a computer system will ultimately raise the price of the system.
Another problem arises as a result of the direction the computer industry has taken in the adoption of an IOP “standard”. Currently, the computer industry is pushing to adopt the Intel i960 processor for the industry standard I
2
O IOP. Some of the problems with the i960 include computing and speed problems, especially when the i960 is compared to other existing processors on the market.
Therefore, while I
2
O is a significant improvement in increasing the overall speed of computer systems, an efficient implementation of I
2
O is necessary to realize maximum gains. The present invention utilizes software to partition the multiple processors so that at least one of the host processors is dedicated to controlling I/O. The present invention further makes a computer system I
2
O compliant by providing a special software driver to perform the allocation and control of host processors for functions such as those controlled by a typical IOP.
SUMMARY OF THE INVENTION
The present invention overcomes the above identified problems as well as other shortcomings and deficiencies of existing technologies by providing a method and apparatus for partitioning processors on a multiprocessor machine. The present invention performs the partitioning using a software driver. The host processors are partitioned, leaving at least one host processor for providing operating system functions, and allocating one or more target processors to perform other functions such as those of a typical IOP. The present invention allocates and totally controls processors, placing the target processors under the control of application-specific software instead of leaving them under the direct control of the operating system.
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Mendel, Brett; “Server I/O all set to flow”;Lantimes, Oct. 27, 1997, vol. 14, Issue 22; cover page and p. 31.
Briggs, Chris; “Smarter and Faster I/O for Servers”; CORE: Operating Systems;Byte, May 1, 1996, vol. 2, No. 5.
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I2O Introduction; Technology Bac
Compaq Computer Corporation
Eng David Y.
Fletcher Yoder & Van Someren
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