Method and apparatus for providing multiple clock signals on...

Details Method and apparatus for providing multiple clock signals on... Method and apparatus for providing multiple clock signals on...

2001-03-21

2004-09-28

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06798257

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronic circuitry and phase-locked loops; and more particularly, the invention relates to providing multiple clock signals on a chip using a second phase-locked loop (PLL) library circuit connected to a buffered reference clock output of a first PLL library circuit.
BACKGROUND OF THE INVENTION
Application-specific integrated circuits (ASICs) have increasingly added internal PLLs to achieve high-frequency internal clocks, and adjust internal clock edges at the input of the internal flip-flops to match the edges of the external clocks. The aligning of these internal clocks with the external clocks allows high-frequency external interfaces to communicate with the ASIC.
Most ASIC vendors provide PLL library circuits or macros that support internal reference clocks and PLL library circuits or macros that support external-capable reference clocks. For example, illustrated in
FIG. 1A
is a block diagram of a prior art library PLL circuit
110
(IBM's PLL7SLIBE) receiving a reference clock from an external source. As shown, prior art library PLL circuit
100
provides for an external reference clock input
109
, a buffered reference clock output
105
which is a non-inverted representation of the signal received at reference clock input
109
, and three phase-locked loop clock outputs
101
-
103
.
Illustrated in
FIG. 1B
is a block diagram of a prior art library PLL circuit
110
receiving a reference clock from an internal source. As shown, prior art library PLL circuit
110
provides for an external reference clock input
119
, a buffered reference clock output
115
, and three phase-locked loop clock outputs
111
-
113
.
FIG. 1C
further illustrates these library circuits
100
and
110
(
FIGS. 1A-B
) by providing a prior art low-level block diagram of the PLL circuit
150
used in library circuits
100
and
110
. As shown, prior art library PLL circuit
150
provides for a reference clock input
159
, a buffered reference clock output
165
which is a non-inverted representation of the signal received at reference clock input
159
, and three phase-locked loop clock outputs
171
-
173
.
The documentation on these library circuits teaches that when using the PLL7SLIBE library circuit
100
(FIG.
1
A), REFCLK input
109
connects directly to a chip pad, while when using the PLL7SLIBI library circuit
110
(FIG.
1
B), REFCLK input
119
typically connects to the output of a receiver. BUFREFCLK
105
and
115
(
FIGS. 1A and 1B
) are a buffered version of the reference clock input to the PLL
100
and
105
at respective REFCLK inputs
109
and
119
. The use of BUFREFCLK
105
and
115
are optional, but they are available for applications that need the REFCLK signal for other functions. The mechanisms and characteristics of the internal logic used to generate the signals produced from BUFREFCLK
105
and
115
are typically not disclosed, and thus, the exact nature of these signals produced are questionable.
Typically, in PLL library circuits, such as those illustrated in
FIGS. 1
A-B and
2
, the skew (i.e., difference in edge-adjustment capability) is a function of, inter alia, the input delay through the I/O cell of the reference clock of the internal PLL, the trace length, and process effects. The external-reference PLL is typically only limited by the pin-die delay, and that is less process-variant, and is adjusted for in the layout.
Certain applications require the uses of clocks at multiple frequencies. In some cases, these multiple clock signals are produced by a single PLL or by receiving multiple clock signals from external sources. Especially because of the prohibitive cost of multiple reference clocks and the excessive loading by multiple PLLs using the same external reference (e.g., either both internal PLLs use the same output of an input buffer, or both external PLLs use two pin inputs to bring in the reference clock which increases the load of the clock on the board or doubles the number of clocks to provide to each ASIC), needed are new methods and systems for providing multiple clock signals on a chip.
SUMMARY OF THE INVENTION
Apparatus and methods are disclosed for providing multiple clock signals on a chip using a second phase-locked loop (PLL) library circuit connected to a buffered reference clock output of a first PLL library circuit. One embodiment comprises a first phase-locked loop circuit including an off-chip reference clock input, one or more phase-locked loop clock outputs, and a buffered reference clock output. The embodiment additionally comprises a second phase-locked loop circuit including an on-chip reference clock input and one or more phase locked loop clock outputs, wherein the buffered reference clock output of the first phase-locked loop circuit is electrically coupled to the on-chip reference clock input of the second phase-locked loop circuit.


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“Phase-Locked Loop,” ASIC SA-27 Databook, Document No. SA14-2214-02, IBM Corp., Aug. 24, 1999, pp. 825-866.
“Phase-Locked Loop,” ASIC SA-27 Databook, Document No. SA14-2214-02, IBM Corp., Nov. 10, 2000, pp. 895-936.

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